The technique looks from the "bottom" side of the chip -- so the imaged elements are mostly "metal 1", e.g. the layer of metal that is directly connected to the

The technique looks from the "bottom" side of the chip -- so the imaged elements are mostly "metal 1", e.g. the layer of metal that is directly connected to the transistors. Inserting a dummy layer in between the transistors and metal 1 would be a huge performance and density impact, I don't think it'd be practical. That being said, the back side power delivery stuff that is currently in the pipe for the sub-"2nm" nodes would block viewing the transistors.