3 ms·
You mean memory fences? The big architecture (x86, ARM, RISC-V) all contain instructions for them.
by colejohnson66 3y ago
You mean memory fences? The big architecture (x86, ARM, RISC-V) all contain instructions for them.
- touisteur 3y agoI mean permanently disable all speculative execution on a specific core and reduce/disable all side-channels of the kind. If you're saying I can do through injection of fence instructions between every instruction, coupled with isolcpus... I might have a fun weekend coming playing with Intel Pin. But I'm guessing the performance hit might be worse than 'just' disabling speculative execution on a core - if it was possible at all - or that the fence instructions might not be enough there? Haven't thought it through. But it would be a fun question to ask the likes of Daniel Gruss...
- smallmancontrov 3y agoYep. Memory fences are a sniper rifle, EIEIO+ is a shotgun, and side channel attacks are a knife fight.