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Alibaba claims to launch a server grade RISC-V processor this year

7 points by fork-bomber 2y ago

brucehoult 2y ago
The factuality of this article is pretty dodgy. The C910 core was not launched two years ago, it was launched in July 2019, at the same time as the C906, and just weeks after the RISC-V base ISA (RV64IMAFDC) was officially frozen and published. THead recently said their customers have shipped billions of these cores. The C906 was available earlier with the AWOL Nezha dev board available in around June 2021. A board ("RVB-ICE") with three C910 cores in a low volume test chip became available in November 2021 or so. Two mass-production chips with the C910 (quad core TH1520 and 64 core SG2042) became available in test chips in early 2023 and shipped in volume in July 2023 and January 2024. I'm not sure why the SG2042 would not be regarded as a "server grade" chip. It's similar microarchitecture and cache and clock speed to Amazon's Graviton 1 five years earlier, except with 64 cores instead of 16. Certainly 2nd generation chips will be better, but it's already usable.
Alifatisk 2y ago
Risc-v is cool, I just wish there was an easier way to simulate it and try your code on. At the moment, I use a vscode extension but it’s very limited. The workflow from writing your code to trying it in your microprocessor is slow.
- brucehoult 2y ago
  Weird thing to say! What do you call slow? bruce@i9:~$ cat hello.c #include <stdio.h> int main(){ printf("Hello world!\n"); return 0; } Cross-compiling and running in a local emulator: bruce@i9:~$ time (riscv64-unknown-elf-gcc hello.c -o hello; qemu-riscv64-static ./hello) Hello world! real 0m0.082s user 0m0.025s sys 0m0.010s Cross-compiling, copying to VisionFive 2 board, and running there: bruce@i9:~$ time (riscv64-unknown-elf-gcc hello.c -o hello; scp hello vf:;ssh vf ./hello) hello 100% 23KB 1.9MB/s 00:00 Hello world! real 0m0.812s user 0m0.086s sys 0m0.000s Compiling and running directly on the VisionFive 2: user@starfive:~$ time gcc hello.c -o hello real 0m0.193s user 0m0.149s sys 0m0.044s user@starfive:~$ time ./hello Hello world! real 0m0.006s user 0m0.002s sys 0m0.004s So cross compile and emulate on i9-13900HX is about twice faster than native compile and native run directly on the $50 RISC-V board ... under 0.1s vs almost exactly 0.2s. Adding in two invocations of OpenSSH (at ~0.35s each) to cross compile then run on the board does make it slower, but it's still under 1 second. This becomes the preferred method for very large programs.
  - Alifatisk 2y ago
    I appreciate the examples you sent, I don't know why I didn't think of using the qemu emulator! The codebase I was in didn't use C but were pure risc-v assembly. The workflow from each change to running it consisted of the following steps: - Make your change (not too because you want to easily see when something went wrong) - Run the build script that compiles the code and sends it to the microcontroller - Restart the microcontroller - See the change This is what I had to do on every change I did on the code, debugging was even harder because I couldn't directly print out to the console because it was running on a microcontroller, not on my laptop. Your suggestions might improve the workflow further though. The closest thing I could get to debugging was to replicate the relevant assembly in vscode and using the risc-v simulator and walk through each step. But comparing this experience with, let's say, how you develop in Flutter, the feedback is instant.

7 points by fork-bomber 2y ago

The factuality of this article is pretty dodgy. The C910 core was not launched two years ago, it was launched in July 2019, at the same time as the C906, and just weeks after the RISC-V base ISA (RV64IMAFDC) was officially frozen and published. THead recently said their customers have shipped billions of these cores. The C906 was available earlier with the AWOL Nezha dev board available in around June 2021. A board ("RVB-ICE") with three C910 cores in a low volume test chip became available in November 2021 or so. Two mass-production chips with the C910 (quad core TH1520 and 64 core SG2042) became available in test chips in early 2023 and shipped in volume in July 2023 and January 2024. I'm not sure why the SG2042 would not be regarded as a "server grade" chip. It's similar microarchitecture and cache and clock speed to Amazon's Graviton 1 five years earlier, except with 64 cores instead of 16. Certainly 2nd generation chips will be better, but it's already usable.

Alifatisk 2y ago

Risc-v is cool, I just wish there was an easier way to simulate it and try your code on. At the moment, I use a vscode extension but it’s very limited. The workflow from writing your code to trying it in your microprocessor is slow.

brucehoult 2y ago
Weird thing to say! What do you call slow? bruce@i9:~$ cat hello.c #include <stdio.h> int main(){ printf("Hello world!\n"); return 0; } Cross-compiling and running in a local emulator: bruce@i9:~$ time (riscv64-unknown-elf-gcc hello.c -o hello; qemu-riscv64-static ./hello) Hello world! real 0m0.082s user 0m0.025s sys 0m0.010s Cross-compiling, copying to VisionFive 2 board, and running there: bruce@i9:~$ time (riscv64-unknown-elf-gcc hello.c -o hello; scp hello vf:;ssh vf ./hello) hello 100% 23KB 1.9MB/s 00:00 Hello world! real 0m0.812s user 0m0.086s sys 0m0.000s Compiling and running directly on the VisionFive 2: user@starfive:~$ time gcc hello.c -o hello real 0m0.193s user 0m0.149s sys 0m0.044s user@starfive:~$ time ./hello Hello world! real 0m0.006s user 0m0.002s sys 0m0.004s So cross compile and emulate on i9-13900HX is about twice faster than native compile and native run directly on the $50 RISC-V board ... under 0.1s vs almost exactly 0.2s. Adding in two invocations of OpenSSH (at ~0.35s each) to cross compile then run on the board does make it slower, but it's still under 1 second. This becomes the preferred method for very large programs.
- Alifatisk 2y ago
  I appreciate the examples you sent, I don't know why I didn't think of using the qemu emulator! The codebase I was in didn't use C but were pure risc-v assembly. The workflow from each change to running it consisted of the following steps: - Make your change (not too because you want to easily see when something went wrong) - Run the build script that compiles the code and sends it to the microcontroller - Restart the microcontroller - See the change This is what I had to do on every change I did on the code, debugging was even harder because I couldn't directly print out to the console because it was running on a microcontroller, not on my laptop. Your suggestions might improve the workflow further though. The closest thing I could get to debugging was to replicate the relevant assembly in vscode and using the risc-v simulator and walk through each step. But comparing this experience with, let's say, how you develop in Flutter, the feedback is instant.