zig: yes, it's very interesting. there's other parts i'm not sold about, but that idea is very interesting. spinalHDL: yes, also interesting. although honestly

zig: yes, it's very interesting. there's other parts i'm not sold about, but that idea is very interesting. spinalHDL: yes, also interesting. although honestly, i really prefer SV. it's a shame that the language has become so complex, but a synthesizable subset still ends up being the best thing for me to efficiently describe hardware. what they did with generate() and parameterization (borrowed from VHDL?) is very nice. it's far, far, better than C++ templates for an analogous purposes. i very rarely need to use `if, `define in SV nowadays. cpp: oh yes, i'm a nerd about languages/macros/meta-programming/etc.