Yeah, I completely agree. RISC vs CISC needs to be buried. It’s interesting to hear stories from the actual designers of CISC chips, because they talk about th

Yeah, I completely agree. RISC vs CISC needs to be buried. It’s interesting to hear stories from the actual designers of CISC chips, because they talk about the things that they did to try and make their chips faster and more useful. “Lots of addressing modes” is one of them, and it kinda turns out the future is to have fewer addressing modes. And the reasoning for it is kinda interesting. Like, imagine that you have a memory indirect addressing mode, and decide to throw an increment on there for good measure. That’s cool and all, but most compilers never figured out how to generate those instructions, and you can get two page faults from a single damn instruction. Kinda makes it hard to deal with exceptions correctly. There are also a few bad ideas that came out of the natural evolution of RISC doctrines. Non-interlocked instructions and hazards, VLIW for general-purpose CPUs, a few others. I think in general, if you expose too little of the details of how your CPU works you sabotage anyone trying to write fast code, and if you expose too much of the details, you sabotage your ability to ship a new CPU that works differently.