>"Instruction set summary Figure 5.2 shows FRISC 3's four instruction formats: one for control flow, one for memory loads and stores, one for ALU operations, a

>"Instruction set summary Figure 5.2 shows FRISC 3's four instruction formats: one for control flow, one for memory loads and stores, one for ALU operations, and one for shift operations. The FRISC 3 uses unencoded instruction formats similar in spirit to those found on the NC4016, RTX 2000, and M17. All instruction formats use the highest 3 bits of the instruction to specify the instruction type." Seems to me that an FRISC CPU could easily be implemented on even the most minimal of FPGA's... an ASIC or even 7400-series logic implementation would not be that challenging -- at least compared to other more complex CPU designs... Related: https://academia.stackexchange.com/questions/209300/when-teaching-computer-architecture-why-are-universities-using-obscure-or-even https://academia.stackexchange.com/questions/209300/when-tea... >"o The whole FRISC reference manual was 4 pages long. The print version of Wikibooks x86 Assembly has 90 pages. Intel 80286 (processor picked at random) reference manual has 513 pages. We were allowed to have a copy of the manual in the exams, and I had a much easier time searching through a paper copy of 4 pages than 513 (and it was also much lighter to carry around). o The textbook based on FRISC came out in 2002, and a second edition in 2004. The instruction set never changed. x86 was developed based on the Intel 8086 microprocessor, in 1978, and the instruction set underwent constant changes and additions o FRISC will never be out of date -- it will always be a perfectly valid, functional, microprocessor designed primarily for simplicity and teaching purposes. Neither x86 nor ARM assembly have been designed with simplicity in mind; and which ever instruction set you select, there is a good chance you'll be hopelessly out of date in a few years." https://ivanzuzak.info/FRISCjs/webapp/ https://ivanzuzak.info/FRISCjs/webapp/