4 ms·
It's RISC-V that's MIPS-ish, not the other way around.
by NonEUCitizen 3y ago
It's RISC-V that's MIPS-ish, not the other way around.
- brucehoult 3y agoLater MIPS ISA revisions were after RISC-V and appeared to copy RISC-V features, such as compare-two-registers-and-branch in MIPSr6 (2014) and other things including the variable length encoding in the just about still-born nanoMIPS which I think has made it into only one SoC used exclusively by Mediatek.
- snvzz 3y agoMIPS was RISC[0]-ish. So is RISC-V. 0. https://en.wikipedia.org/wiki/Berkeley_RISC#RISC_I https://en.wikipedia.org/wiki/Berkeley_RISC#RISC_I