CPUs with length-agnostic vector ISAs -- so vector register size is an implementation detail and code for 128 bit vector registers runs unchanged (but efficient

CPUs with length-agnostic vector ISAs -- so vector register size is an implementation detail and code for 128 bit vector registers runs unchanged (but efficiently) on 2048 bit registers -- will very soon be competitive with GPUs on GPGPU tasks and better on things needing close coupling between vector and scalar. They might even be quite good as actual GPUs, with instructions for things such as texture interpolation added.