Most FPGAs have various kinds of primitives that can be instantiated manually in the middle of a larger Verilog design. Sometimes those primitives can be used t

Most FPGAs have various kinds of primitives that can be instantiated manually in the middle of a larger Verilog design. Sometimes those primitives can be used to do things that are very hard to make the synthesizer create automatically. In general, the synthesizer will be better than you at anything lookup-table or flip-flop related. Ditto for simple primitives like shift-registers. But it probably doesn't know how to infer the more complicated primitives, and so those are usually done with the Verilog equivalent of inline assembly. For a few tight designs, I've given some hints to the the placer. These are things like grouping components together, or setting location constraints on a few key primitives. That kind of thing isn't too uncommon. I've never seen anybody try to route things manually though.