You mean we'll have hardware accelerated ternary instructions? https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#techs=AVX_512&text=terna

You mean we'll have hardware accelerated ternary instructions? https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#techs=AVX_512&text=ternary&expand=5438,5437 https://www.intel.com/content/www/us/en/docs/intrinsics-guid... (Okay probably those are not ready to be used as NN weights if the activations are not binary too, but... the gap to what CPUs already can do is getting smaller.)