Context: Historic computer problem: The speed/bandwidth bottleneck between a computer's CPU and main memory... >"The 2 TB Pooled CXL Memory system is a 2U rac

Context: Historic computer problem: The speed/bandwidth bottleneck between a computer's CPU and main memory... >"The 2 TB Pooled CXL Memory system is a 2U rack-mountable machine built by H3 with eight 256 GB Samsung CXL memory modules connected using XConn's XC50256 CXL 2.0 switch supporting 256 PCIe Gen5 lanes and 32 ports." Which leads to this page: https://www.xconn-tech.com/product https://www.xconn-tech.com/product >"CXL 2.0 and PCIe Gen5 Switch IC, 256 lanes with total 2,048GB/s switching capacity" Phrased another way: 2,048GB/s of potential CPU-to-Main-RAM bandwidth -- if the CPU is specifically designed for it (i.e. IBM was apparently designing a Power10 or Power 11 CPU(?) to work with an OpenCAPI open memory interface -- of which OpenCAPI was apparently folded into the CXL spec / CXL Consortium...) This is important, because in the future, we're probably going to be seeing a lot more CXL CPU's and high bandwidth CXL Switches (by other companies) linking to main memory (which will also be or become CXL), appear... Related: Optical CXL Switches: https://www.forbes.com/sites/tomcoughlin/2023/08/16/optical-pciecxl-interconnects-and-new-wdc-nvme-products https://www.forbes.com/sites/tomcoughlin/2023/08/16/optical-... "Building The Perfect Memory Bandwidth Beast": https://www.bittware.com/resources/cxl/ https://www.bittware.com/resources/cxl/ Google query: "CXL FPGA": https://www.google.com/search?q=CXL+FPGA https://www.google.com/search?q=CXL+FPGA Github curated list: "Awesome-CXL-Open-Source": https://github.com/huangyibo/Awesome-CXL-Open-Source https://github.com/huangyibo/Awesome-CXL-Open-Source CXL Specification: https://computeexpresslink.org/cxl-specification/ https://computeexpresslink.org/cxl-specification/