3 ms·
I would guess they (a) want soft realtime performance, and (b) would not want to introduce something critical that could interfere with debuggability or potent
by robocat 3y ago
I would guess they (a) want soft realtime performance, and (b) would not want to introduce something critical that could interfere with debuggability or potentially reliability. I'd never do it unless it was the last choice available. Virtual paging is nasty and I wouldn't want the doubt.
- monocasa 3y agoI think they're just trying to keep it simple (which is totally fair, KISS principle is valuable). You can keep soft real time perf with this scheme, just like you can keep soft realtime perf on any system with a soft fill TLB. I say all of this as I used to be the lead for a real time kernel that would allow more than 8 regions on a task on a Cortex-M0/M3. It's pretty easy to hit that amount with a combo of fine grain access (you probably want your RO section different than your TEXT section, you probably want your stack discontiguous with any mapped section, you've got all of your MMIO regions your task cares about which necessitate other MPU regions because the difference between normal memory and device memory is configured by the MPU), combined with breaking some apart to get greater granularity/packing like they talk about here.