3 ms·

FWIW, you can support more than 8 regions by treating that hardware more like a soft fill TLB.

by monocasa 3y ago

packetlost 3y ago
I assume TLB is translation lookaside buffer, but what do you mean by "soft fill" here?
- Veserv 3y ago
  They mean software-filled. On “page fault (really a illegal memory access)” you walk a software data structure to determine if there should actually be accessible memory there then you “page in (update the MPU to make the memory accessible, possibly evicting another entry)” the memory. This is how some older chips used to work. Hardware page table walkers can be viewed as just a hardware implementation of such code.
  - chc4 3y ago
    I was horrified to learn that PowerPC uses an "inverted page table", which is essentially just a TLB implemented as a hash table. If the requested page isn't resident in the inverted page table it delivers an interrupt, where the kernel is supposed to walk it's own internal internal page table data structure and populate the hash table entry for the missing page. It was a big surprise coming from x86 or ARM on personal computer kernels where they have a fully populated page table as the canonical source of mappings, and all walking in hardware!
    - saagarjha 3y ago
      It does let you do some cute things in the software implementation though. I’d prefer a hardware walk of course but if I can’t have it might as well enjoy things.
robocat 3y ago
I would guess they (a) want soft realtime performance, and (b) would not want to introduce something critical that could interfere with debuggability or potentially reliability. I'd never do it unless it was the last choice available. Virtual paging is nasty and I wouldn't want the doubt.
- monocasa 3y ago
  I think they're just trying to keep it simple (which is totally fair, KISS principle is valuable). You can keep soft real time perf with this scheme, just like you can keep soft realtime perf on any system with a soft fill TLB. I say all of this as I used to be the lead for a real time kernel that would allow more than 8 regions on a task on a Cortex-M0/M3. It's pretty easy to hit that amount with a combo of fine grain access (you probably want your RO section different than your TEXT section, you probably want your stack discontiguous with any mapped section, you've got all of your MMIO regions your task cares about which necessitate other MPU regions because the difference between normal memory and device memory is configured by the MPU), combined with breaking some apart to get greater granularity/packing like they talk about here.

FWIW, you can support more than 8 regions by treating that hardware more like a soft fill TLB.

packetlost 3y ago

I assume TLB is translation lookaside buffer, but what do you mean by "soft fill" here?

Veserv 3y ago
They mean software-filled. On “page fault (really a illegal memory access)” you walk a software data structure to determine if there should actually be accessible memory there then you “page in (update the MPU to make the memory accessible, possibly evicting another entry)” the memory. This is how some older chips used to work. Hardware page table walkers can be viewed as just a hardware implementation of such code.
- chc4 3y ago
  I was horrified to learn that PowerPC uses an "inverted page table", which is essentially just a TLB implemented as a hash table. If the requested page isn't resident in the inverted page table it delivers an interrupt, where the kernel is supposed to walk it's own internal internal page table data structure and populate the hash table entry for the missing page. It was a big surprise coming from x86 or ARM on personal computer kernels where they have a fully populated page table as the canonical source of mappings, and all walking in hardware!
  - saagarjha 3y ago
    It does let you do some cute things in the software implementation though. I’d prefer a hardware walk of course but if I can’t have it might as well enjoy things.

robocat 3y ago

I would guess they (a) want soft realtime performance, and (b) would not want to introduce something critical that could interfere with debuggability or potentially reliability. I'd never do it unless it was the last choice available. Virtual paging is nasty and I wouldn't want the doubt.

monocasa 3y ago
I think they're just trying to keep it simple (which is totally fair, KISS principle is valuable). You can keep soft real time perf with this scheme, just like you can keep soft realtime perf on any system with a soft fill TLB. I say all of this as I used to be the lead for a real time kernel that would allow more than 8 regions on a task on a Cortex-M0/M3. It's pretty easy to hit that amount with a combo of fine grain access (you probably want your RO section different than your TEXT section, you probably want your stack discontiguous with any mapped section, you've got all of your MMIO regions your task cares about which necessitate other MPU regions because the difference between normal memory and device memory is configured by the MPU), combined with breaking some apart to get greater granularity/packing like they talk about here.