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Guys....what are the instructions? The on-chip memory they are talking about is essentially...a big register set. So we have load from main memory into regist
by rhelz 3y ago
Guys....what are the instructions? The on-chip memory they are talking about is essentially...a big register set. So we have load from main memory into registers, store from registers into main memory, multiply matrices--source and dest are stored in registers....
We have a 20 instruction, load-store cpu....how is this not RISC? At least RISC how we used the term in 1995?
- dmoy 3y agoI think the "multiply matrices" instruction is the one that makes it a cisc
- brigade 3y agoIts design follows the old idea that an ISA should be designed for assembly programmers; that instructions should implement complex or higher-level functions intended for a programmer to use directly. RISC rejected that notion (among other things) and focused on designing ISAs for a compiler to target when compiling high level languages, without wasting silicon on instructions a compiler cannot easily use. For the TPU, a compiler cannot easily take a 256x256 matrix multiply written in a high-level language like C and emit a Matrix_Multiply instruction.
- Symmetry 3y agoI don't think it makes any sense to talk about all on-chip memory as a register set. In practice most uses of REP MOVS these days don't leave L3$ but because it's an instruction that runs for a highly variable amount of time while transferring data between different locations we consider it very CISCy. And the TPU also has instructions to transfer data over PCIe to and from the TPU's local DDR3 memory as well, which isn't on the chip and I hope you would agree that it's not like a register at that point. If every instruction was always one 256 element unit maybe you could make the analogy stick. But it's working with 256*N element operations.