I don't think they disclosed their algorithms but both Cadence Spectre-X and Mentor AFS-XT have an "improved" RC matrix solver as they market it. I think Spectr

I don't think they disclosed their algorithms but both Cadence Spectre-X and Mentor AFS-XT have an "improved" RC matrix solver as they market it. I think Spectre-X was launched at DAC 2019, but I've been using it since 2018. AFS-XT is launched couple of years ago as a response. The main goal of RC reduction is post-layout simulation. With these simulators what you would see in the results is there is a primitive called RC, which doesn't exist in the netlist. You need to define an fmax of the circuit, and it will reduce RC routing parasitics to approximately create same delays within that frequency range with a much more reduced matrix. Netlisting take some time but simulation is like 10x faster due to this reduction. I'm mainly using FinFET processes, so each transistor comes with tens of parasitics annotated. For a moderately large design it's normal to have millions of R and C. There are also tools doing this on the extracted netlist directly by the way. Cadence's tool is called Quantus Standalone Reduction (qreduce).