Mate. You reference some random unspecified articles on the internet. The internet has thigs of widely varying quality and accuracy. If they are claiming to kno

Mate. You reference some random unspecified articles on the internet. The internet has thigs of widely varying quality and accuracy. If they are claiming to know e.g. what Apple's contract terms are with Arm then they almost certainly don't have any actual information. > I did some more reading last night. Great nice. I'm glad you're researching RISC-V. Welcome aboard. I've been heavily involved in RISC-V since late 2016 when I bought my first board. In 2017 I co-authored a conference paper on a high performance emulator for RISC-V on x86_64. In early 2018 I started working for RISC-V pioneers SiFive -- my H-1B visa paperwork says they have 32 employees. It was under 20 the first time in was in their office for a quiet chat (which turned out to be the job interview). You'll find my name in the acknowledgements in the RISC-V User-level ISA Manual, and also the specs for the Bitmanip and Vector extensions. I was heavily involved for example in writing the example RVV code in the manual, adding support for the needed V instructions to the Spike emulator, being on the working group designing the V instructions, and modifying both example code and emulator to track changes in the ISA design, which were quite radical pre draft 0.7. I was also around when that memory consistency model was being developed, though not directly involved. RISC-V got world-class experts in academia and industry to design that. Other ISAs probably just get a few company employees to bang something out, and try to fix it up later when academic research points out problems.