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ForwardCom – An open forward-compatible instruction set architecture (ISA)
- peter_d_sherman 3y agoFrom the following link/page: https://agner.org/optimize/#instructionset https://agner.org/optimize/#instructionset >"ForwardCom: An open standard instruction set for high performance microprocessors This is a proposal and discussion of how an ideal instruction set architecture can be constructed. The proposed instruction set combines the best from the RISC and CISC principles to produce a flexible, consistent, modular, orthogonal, scalable and expansible instruction set for high performance microprocessors and large vector processors. The ForwardCom instruction set has variable-length vector registers and a special addressing mode that allows the software to automatically adapt to different microprocessors with different maximum vector lengths and make efficient loops through arrays regardless of whether the array size is divisible by the vector length. Standardization of the corresponding ecosystem of ABI standards, function libraries, compilers, etc. makes it possible to combine different programming languages in the same program." I found this page searching for a list of all CPU IPC counts (Instructions Per Cycle a.k.a. "Instructions Per Clock": https://en.wikipedia.org/wiki/Instructions_per_cycle https://en.wikipedia.org/wiki/Instructions_per_cycle) because I wanted to determine which CPU or CPUs are the current record holders in terms of max IPC -- maximum Instructions Per Cycle... But apparently IPC is only part of the story... IPC depends, among other things, on a CPU's Instruction Set Architecture (ISA), so: creating an ISA specifically for Max IPC ...seems to make a lot of sense! (Hence, Agner Fog's ForwardCom ISA page -- as referred to by this post...)