VLIW is what the Unison project (the context behind this post) was attacking. https://unison-code.github.io/ https://unison-code.github.io/ My best understandin

VLIW is what the Unison project (the context behind this post) was attacking. https://unison-code.github.io/ https://unison-code.github.io/ My best understanding is that exposing the details of the CPU to the compiler via a more complex ISA has not worked that well. Possibly because the compilation problem just gets too hard, but maybe also for momeentum and ecosystem reasons. I think another lesson is that it is unwise to make your isa expose microarchitecture because microarchitecture changes quite a bit between generations and inidividual CPUs. Things like delay slots seem like misfeatures now.