I thought the paper wasn't a simulation? They refer to the CXL memories as "hard IP" and "soft IP", so two ASICs and and FPGA. You could also imagine a DMA en

I thought the paper wasn't a simulation? They refer to the CXL memories as "hard IP" and "soft IP", so two ASICs and and FPGA. You could also imagine a DMA engine within the CXL ASIC to assist with paging things in and out of main memory in an asynchronous fashion.