It seems like the chips are speculating past a 'lock cmpxchgq', which corresponds to a seq-cst access (IIRC). > or the acquire barrier must not be stalling lat

It seems like the chips are speculating past a 'lock cmpxchgq', which corresponds to a seq-cst access (IIRC). > or the acquire barrier must not be stalling later memory accesses That is my impression. But I am really confused about this stuff in general.