If you are doing hardware verification, more than using IP blocks in the space, verification tasks are typically oriented around 1. Design : architectures need

If you are doing hardware verification, more than using IP blocks in the space, verification tasks are typically oriented around 1. Design : architectures need to be well constructed 2. Well derived tests on case-elements/state-conditions : asserting that a specific signal-value achieves a specific state at a specific time is not hard, but coming up with the conditions are. 3. Placement & technology specific details of delays, glitch management & etc. Event-driven simulators are essentially doing a lot of simple things correctly, so the language doesn't need to be full-featured, ideally it is as efficient as possible in computation, since checking the verification takes the most time for complex systems. Additionally after logic has been verified, there are many physical implementation details that have to be layered on top of this, including placement & route optimizations. Veryl to me looks like a SystemVerilog competitor in Rust-like language aspects.