6 ms·

I was going through all the alternative HDLs the other day to see what’s out there. So many one off projects to appeal to this language or that language, but no

I was going through all the alternative HDLs the other day to see what’s out there. So many one off projects to appeal to this language or that language, but none solving real problems in the space. The problem? Modeling large systems with modules with large I/O (DSPs or something else) and verifying those things is hard and not well suited for a complex verbose language. Fight me, but I really think a mathworks simulink type visual modeling environment is a better way to approach this problem (and I hate mathworks with a passion, this isn’t a plug for matlab). That type of environment coupled with a way to generate high quality HDL is what I really want. I know mathworks has HDL coder and it’s ok, but still doesn’t quite do everything and you have the pay the enormous mathworks fee and can’t crowdsource platform updates as well as a well managed open source project might be able offer. So when I see stuff like this I think “cool” but also “why???”

omgJustTest 3y ago
If you are doing hardware verification, more than using IP blocks in the space, verification tasks are typically oriented around 1. Design : architectures need to be well constructed 2. Well derived tests on case-elements/state-conditions : asserting that a specific signal-value achieves a specific state at a specific time is not hard, but coming up with the conditions are. 3. Placement & technology specific details of delays, glitch management & etc. Event-driven simulators are essentially doing a lot of simple things correctly, so the language doesn't need to be full-featured, ideally it is as efficient as possible in computation, since checking the verification takes the most time for complex systems. Additionally after logic has been verified, there are many physical implementation details that have to be layered on top of this, including placement & route optimizations. Veryl to me looks like a SystemVerilog competitor in Rust-like language aspects.
- bb88 3y ago
  > Additionally after logic has been verified, there are many physical implementation details that have to be layered on top of this, including placement & route optimizations Software designed chip fabrication. Please someone make this happen in my lifetime.
  - duskwuff 3y ago
    > Software designed chip fabrication. Please someone make this happen in my lifetime. That's already a thing. See, for instance, https://platform.efabless.com/shuttles/MPW-8 https://platform.efabless.com/shuttles/MPW-8 Most of it uses the same languages, and many of the same tools, as FPGA design.
stefanpie 3y ago
Funnily enough, Matlab offers a high-level synthesis (HLS) tool to lower Matlab code and Simulink models to Verilog [1]. I have not personally used it, but the last I heard, it works well enough for those who need it and Matlab puts in the work to support it. However, HLS is another whole can of worms, and it can be confusing when discussing new HDLs and the distinction between an HLS tools and high-level HDL dialects. [1] https://www.mathworks.com/discovery/high-level-synthesis.html https://www.mathworks.com/discovery/high-level-synthesis.htm...
- pclmulqdq 3y ago
  Matlab HLS is fantastic due to the restricted problem space. The C-to-hardware HLS stuff often has more mixed results.

omgJustTest 3y ago

If you are doing hardware verification, more than using IP blocks in the space, verification tasks are typically oriented around 1. Design : architectures need to be well constructed 2. Well derived tests on case-elements/state-conditions : asserting that a specific signal-value achieves a specific state at a specific time is not hard, but coming up with the conditions are. 3. Placement & technology specific details of delays, glitch management & etc. Event-driven simulators are essentially doing a lot of simple things correctly, so the language doesn't need to be full-featured, ideally it is as efficient as possible in computation, since checking the verification takes the most time for complex systems. Additionally after logic has been verified, there are many physical implementation details that have to be layered on top of this, including placement & route optimizations. Veryl to me looks like a SystemVerilog competitor in Rust-like language aspects.

bb88 3y ago
> Additionally after logic has been verified, there are many physical implementation details that have to be layered on top of this, including placement & route optimizations Software designed chip fabrication. Please someone make this happen in my lifetime.
- duskwuff 3y ago
  > Software designed chip fabrication. Please someone make this happen in my lifetime. That's already a thing. See, for instance, https://platform.efabless.com/shuttles/MPW-8 https://platform.efabless.com/shuttles/MPW-8 Most of it uses the same languages, and many of the same tools, as FPGA design.

stefanpie 3y ago

Funnily enough, Matlab offers a high-level synthesis (HLS) tool to lower Matlab code and Simulink models to Verilog [1]. I have not personally used it, but the last I heard, it works well enough for those who need it and Matlab puts in the work to support it. However, HLS is another whole can of worms, and it can be confusing when discussing new HDLs and the distinction between an HLS tools and high-level HDL dialects. [1] https://www.mathworks.com/discovery/high-level-synthesis.html https://www.mathworks.com/discovery/high-level-synthesis.htm...

pclmulqdq 3y ago
Matlab HLS is fantastic due to the restricted problem space. The C-to-hardware HLS stuff often has more mixed results.