4 ms·
I doubt it. Toolkits like TensorRT are specifically optimised, and NVIDIA already segregated their HPC vs gaming dies (and corresponding, die space). The H100s
by dannyw 3y ago
I doubt it. Toolkits like TensorRT are specifically optimised, and NVIDIA already segregated their HPC vs gaming dies (and corresponding, die space).
The H100s feature a minuscule amount of ROPs and TMUs (mainly for graphics); and doesn’t come with NVENC/DEC, etc. DirectX, Vulkan is not supported.
You’ll just see more and more tensor cores, optimised CUDA cores for bfloat, etc.
- paulmd 3y agoH100 does have NVDEC and jpeg ingest accelerators https://www.servethehome.com/wp-content/uploads/2023/10/NVIDIA-H100-SXM-PCIe-and-NVL-Spec-Table.jpg https://www.servethehome.com/wp-content/uploads/2023/10/NVID... Tbh it’s mildly surprising they even removed NVENC considering the overall size of the chip (in the absolute we are only talking about low-single-digit mm2 savings) and then H100 is still advertised and has features targeting VM graphics/visualization still… remember they also still put a full graphics pipeline with ROPs/TMUs on the chip, just no actual display hardware.
- lobochrome 3y agoIt's a tradeoff with verification and validation, not so much die-space. If you include the IP, you need to run an expensive (time-consuming) simulation and emulation for the IP. Then, you need to validate it on first silicon and pray that it doesn't impact yield in HVM. These days, simulation runs basically nonstop on all the FPGAs the company is able to throw at it until tape out. Then, in post-silicon validation, you have engineering teams working 24/7 to validate the device on the bench. Finally, test engineering tries to achieve yield in HVM. Anything that you don't need on the spec sheet or the designer insists on is cut to save time to market.
- eoerl 3y agoThese can also be used for machine learning actually (see Dali for data loading for instance)