3 ms·

Does anyone know why some of the balls in the (render pics) are missing around the edges? Unrelated: Would this be suitable for a CV system eg in robotics? Eg

Does anyone know why some of the balls in the (render pics) are missing around the edges? Unrelated: Would this be suitable for a CV system eg in robotics? Eg do the realtime stuff on the Cortex-M, and run a linux + OpenCV/OpenVINO etc on the Cortex-A?

adrian_b 3y ago
This is how it is intended to be used (real-time tasks on the Cortex-M, Linux on the Cortex-A). Nevertheless its 64-bit core is optimized for low-power, so it also has low performance. If the applications intended to run under Linux are more demanding, one may need at least some SoC with Cortex-A55 cores (e.g. from NXP), if not one with medium-size cores, like the RK3588 (with quadruple Cortex-A76 + GPU + NPU + some Cortex-M) or one of the overpriced SoCs from Mediatek, Qualcomm or NVIDIA (these latter 3 have worse price/performance than Intel/AMD CPUs). Unless a price under $100 is a condition, the easiest way to make a CV system for robotics is by using one of the very small computers that are available with Intel N100 CPUs (there are models much smaller than a NUC, either at a Pico-ITX size or even smaller, while prices are under $200).
Zeetah 3y ago
The balls are missing to enable making connections to inner balls in a board with fewer layers. The outer balls take up space and so block the traces from inner balls. By strategically removing some of the outer balls, you create channels that can be used for routing taxes from the inner balls.
- the__alchemist 3y ago
  That makes sense! I wish I saw this on their MCU line... (Although you can thread a tiny trace between the balls depending on manufacturer, I don't like it!
gaudat 3y ago
It all comes down to cost. These BGA chips have pins under the device unlike older packages like QFP or DIP. The pattern of missing pins is designed so it a fewer signal layers to bring out all the sigal connections in a typical PCB process. Devices with full grids would need more layers or tighter tolerances. The appeal of STM32MP1 is you can put DDR momery with the chip on a 4 layer board. ST even provides the layout.

adrian_b 3y ago

This is how it is intended to be used (real-time tasks on the Cortex-M, Linux on the Cortex-A). Nevertheless its 64-bit core is optimized for low-power, so it also has low performance. If the applications intended to run under Linux are more demanding, one may need at least some SoC with Cortex-A55 cores (e.g. from NXP), if not one with medium-size cores, like the RK3588 (with quadruple Cortex-A76 + GPU + NPU + some Cortex-M) or one of the overpriced SoCs from Mediatek, Qualcomm or NVIDIA (these latter 3 have worse price/performance than Intel/AMD CPUs). Unless a price under $100 is a condition, the easiest way to make a CV system for robotics is by using one of the very small computers that are available with Intel N100 CPUs (there are models much smaller than a NUC, either at a Pico-ITX size or even smaller, while prices are under $200).

Zeetah 3y ago

The balls are missing to enable making connections to inner balls in a board with fewer layers. The outer balls take up space and so block the traces from inner balls. By strategically removing some of the outer balls, you create channels that can be used for routing taxes from the inner balls.

the__alchemist 3y ago
That makes sense! I wish I saw this on their MCU line... (Although you can thread a tiny trace between the balls depending on manufacturer, I don't like it!

gaudat 3y ago

It all comes down to cost. These BGA chips have pins under the device unlike older packages like QFP or DIP. The pattern of missing pins is designed so it a fewer signal layers to bring out all the sigal connections in a typical PCB process. Devices with full grids would need more layers or tighter tolerances. The appeal of STM32MP1 is you can put DDR momery with the chip on a 4 layer board. ST even provides the layout.