3 ms·
+1 on concerns about verilator not supporting X prop. Definitely a big difference between FPGA and ASICs. The lack of X-prop in verilator is one of the reasons
by bunnie 3y ago
+1 on concerns about verilator not supporting X prop. Definitely a big difference between FPGA and ASICs.
The lack of X-prop in verilator is one of the reasons why a lot of OSS hardware designs are risky or unsuitable for ASIC integration... verilator is popular in OSS, and X-prop isn't a problem for FPGA because every bit in an FPGA is guaranteed to start at a known state.
So, Verilator assuming 0 by default instead of X means that a lot of OSS developers get away with bad coding habits that work perfectly in FPGAs, but can't reliably power up in an ASIC.
- Taniwha 3y agoit's a little more than that - as I mentioned above you can assign xs in a case statement (or anywhere you like) as a signal to you synthesis tool when you don't care what value something is - that allows the synthesis tool to make better gates, and to cause simulations to fail if you were wrong about doing that