4 ms·

In the end Sun had it right with Niagara.

by bobim 3y ago

buildbot 3y ago
Kinda, it turns out SMT has lots of security pitfalls and having many tiny single thread cores vs. some heavily threaded cores works better in practice. (I love the niagara chips, I had a T1 and T2 box for a bit!)
ajross 3y ago
So... not really? I mean, The T1/T2 devices are superficially similar, being a "big" collection of "small" cores in an SMP configuration and targeted at datacenter markets. But the ideas behind Niagra weren't about scale per se, it's was about the idea of using extremely wide multithreaded dispatch to get high instruction throughput out of a simple (and thus small) in-order CPU core. Normally you'd expect such a core to spend most of its time getting stalled on DRAM fetches, but with SMT you can usually find another instruction to run from another thread, so the pipeline keeps moving. The Intel E-cores in this device aren't like that at all. They're smaller than the P-cores, but are still comparatively complicated OOO designs intended to avoid avoid stalls via parallel dispatch.
- sillywalk 3y ago
  IBM's POWER also has 4 or 8 SMT threads/core, but with big OoO cores. I'm not sure how they fit in.
  - ajross 3y ago
    > I'm not sure how they fit in. Neither is IBM, to be fair. POWER is in a lot of ways an exercise in "throw as much junk into the part as we can with no thought to efficiency and see what the benchmarks say". But surely the idea is the same: SMT hides memory latency with parallelism just like lots of load/store units do, so why not both? Datacenter loads that IBM cares about are very often fetch-limited (e.g. queries into a database RAM cache are basically guaranteed not to be nicely L1-cache-local), so maybe the numbers work out. Seems wasteful in traditional/consumer scalar loads for sure.
    - sillywalk 3y ago
      > no thought to efficiency and see what the benchmarks say IBM's slides at HotChips say Power10* was designed for energy efficiency, a 3x better than POWER9 for whatever that's worth. Unfortunately, I can't seem to find a TDP for it. Or benchmarks vs x86-64 server in terms of raw performance or performance / watt. *apparently Power10 is not all caps
vardump 3y ago
Niagara-style (at least T1) design would have never worked in an application like this, because it compromised FPU power for the core count. 8 cores shared one FPU! Niagara (all designs) heavily compromised single-thread performance, which could just mean time critical (5G or whatever) threads cannot complete on time. Niagara was an interesting idea, but not great for most applications.
- cryptonector 3y ago
  That's not what GP meant. GP meant that having lots of small cores is the answer.

In the end Sun had it right with Niagara.

by bobim 3y ago

In the end Sun had it right with Niagara.

Kinda, it turns out SMT has lots of security pitfalls and having many tiny single thread cores vs. some heavily threaded cores works better in practice. (I love the niagara chips, I had a T1 and T2 box for a bit!)

ajross 3y ago

So... not really? I mean, The T1/T2 devices are superficially similar, being a "big" collection of "small" cores in an SMP configuration and targeted at datacenter markets. But the ideas behind Niagra weren't about scale per se, it's was about the idea of using extremely wide multithreaded dispatch to get high instruction throughput out of a simple (and thus small) in-order CPU core. Normally you'd expect such a core to spend most of its time getting stalled on DRAM fetches, but with SMT you can usually find another instruction to run from another thread, so the pipeline keeps moving. The Intel E-cores in this device aren't like that at all. They're smaller than the P-cores, but are still comparatively complicated OOO designs intended to avoid avoid stalls via parallel dispatch.

sillywalk 3y ago
IBM's POWER also has 4 or 8 SMT threads/core, but with big OoO cores. I'm not sure how they fit in.
- ajross 3y ago
  > I'm not sure how they fit in. Neither is IBM, to be fair. POWER is in a lot of ways an exercise in "throw as much junk into the part as we can with no thought to efficiency and see what the benchmarks say". But surely the idea is the same: SMT hides memory latency with parallelism just like lots of load/store units do, so why not both? Datacenter loads that IBM cares about are very often fetch-limited (e.g. queries into a database RAM cache are basically guaranteed not to be nicely L1-cache-local), so maybe the numbers work out. Seems wasteful in traditional/consumer scalar loads for sure.
  - sillywalk 3y ago
    > no thought to efficiency and see what the benchmarks say IBM's slides at HotChips say Power10* was designed for energy efficiency, a 3x better than POWER9 for whatever that's worth. Unfortunately, I can't seem to find a TDP for it. Or benchmarks vs x86-64 server in terms of raw performance or performance / watt. *apparently Power10 is not all caps

vardump 3y ago

Niagara-style (at least T1) design would have never worked in an application like this, because it compromised FPU power for the core count. 8 cores shared one FPU! Niagara (all designs) heavily compromised single-thread performance, which could just mean time critical (5G or whatever) threads cannot complete on time. Niagara was an interesting idea, but not great for most applications.

cryptonector 3y ago
That's not what GP meant. GP meant that having lots of small cores is the answer.