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Scaleway launches RISC-V servers
- MaxBarraclough 3y agoInteresting step, their claim of world's first RISC-V servers available in the cloud is true as far as I know. I see they list 3 officially supported GNU/Linux distros: Debian, Ubuntu, Alpine. I wonder how mature these are on RISC-V at this point and whether they're ready for production server usage.
- brucehoult 3y agoMuch more ready for server usage than desktop usage. Linux is Linux. It's hard to go wrong when you're not mucking about with graphics cards and first-person games and things like that.
- MaxBarraclough 3y agoFor server workloads there can still be plenty of non-trivial architecture-specific dependencies besides the core OS itself, such as the JVM and other JIT-based interpreters. Python 'pip' packages, which often have native code dependencies, may also lack official RISC-V builds.
- brucehoult 3y agoAccess to servers such as these, for pennies per hour, will accelerate authors of those packages porting them to RISC-V. It's a lot lower barrier to entry than buying the equivalent board outright for $180. You can also just do `docker run -it riscv64/ubuntu` on your x86 or Mac, at zero incremental cost.
- zozbot234 3y agoYou should be able to use QEMU user-level emulation to run binaries from other architectures on a RISC-V system, while using native code for the rest. Alternately if the code is available and reasonably clean, you could try a RISC-V build yourself. (Obviously not for the JVM and other JIT-dependent stuff - though these ports are ongoing too - but for most smaller projects it should work fine.)
- yjftsjthsd-h 3y agoNitpick: Alpine is a Linux distro, but not a GNU/Linux distro; it uses musl libc and busybox coreutils.
- arcanemachiner 3y agoOr as I've recently taken to calling it, BusyBox plus Linux.
- williadc 3y agoThis is the first time I've seen the correction go the other way.
- deleted 3y ago[deleted]
- pjmlp 3y agoAndroid and ChromeOS are also Linux distributions without GNU.
- nolist_policy 3y agoChromeOS is glibc based.
- pjmlp 3y agoStand corrected, although little else from GNU is exposed to userspace.
- MaxBarraclough 3y agoInteresting, thanks.
- cpswan 3y agoDebian support for RISC-V is presently only in Sid (testing release). So not production ready. When I ask people what it will take to get RISC-V into stable releases the answer is always ‘better access to test hardware’. Hopefully this is a step along the way.
- self 3y agoUbuntu (server) is a lot closer. For example, see the limitations at the end of https://wiki.ubuntu.com/RISC-V/StarFive%20VisionFive%202 https://wiki.ubuntu.com/RISC-V/StarFive%20VisionFive%202 I haven't tried it -- I installed the VF2 Debian fork in April 2023 or so, then switched to SID, and I'm still on that. I think Ubuntu 24.10 will have a lot better support; mainline support for the VF2/JH7110 is almost complete for 6.6: https://rvspace.org/en/project/JH7110_Upstream_Plan https://rvspace.org/en/project/JH7110_Upstream_Plan
- my123 3y agoTH1520 with the XuanTie C910 core. Avoid. That particular platform is really incredibly slow, Cortex-A5x level. And with RVV 0.7.1 instead of 1.0 too.
- nevi-me 3y agoI was going to try the server out until I saw this comment. Which alternative board/computer would you recommend one buy? I'm learning RISC-V assembly with a friend, it'd be great for us to have a machine to tinker with (we'll use ESP-32-Cx for 32-bit).
- b9b10eb736 3y agoStill way better than a VisionFive 2, and more than enough to get your hands in the thing (especially with the hourly pricing). You have to acknowledge that the RISC-V ecosystem isn't as mature as that of ARM64 and AMD64. You don't get the best performance/price ratio with RISC-V (yet). Many extensions were ratified so recently that hardware doesn't even exist (yet). As far as I'm concerned, the LicheePi 4A from Sipeed which is also equipped with a TH1520 offers a decent value for a RISC-V SBC. If you want more performance than that, it's going to cost you a lot more.
- brucehoult 3y agoRight now, you can't get more performance than the TH1520 (C910 cores) and JH7110 (U74 cores) at ANY price. The only thing you can do is get more of the same cores i.e. SG2042 with 64x C910 cores. The same goes for emulation. QEMU on my i9-13900HX laptop is about the same speed on each core, but there I have 24 cores (32 threads). I just compiled gcc 14 natively on both LicheePi 4A (the same as this hosting) and docker/QEMU: i9-13900HX (8 P + 16 E cores) docker running riscv64/ubuntu image real 101m44.472s user 1695m26.395s sys 24m36.671s LicheePi 4A (TH1520 SoC, 4x C910 cores) real 422m41.367s user 1430m56.638s sys 70m17.994s The LicheePi actually used less CPU time, but the i9 won with more cores.
- 3y ago
- Kab1r 3y agoeMMC for cloud seems to me like a dangerous proposition. As far as I know, they do not hold up well to write intensive workloads. I suppose you will need to use networked logging.
- tux3 3y agoScaleway was also early in providing Arm servers, it's cool to see them keep bringing new stuff It's maybe almost too early, given the performance profile of these and the current state of software compat, but the trajectory is definitely there for RISC-V. Wouldn't be surprised to see these compete strongly against ARM servers a few years from now.
- crq-yml 3y agoThis one is probably more for Scaleway to gain experience than for customers to use seriously. Of course, that excuse could be true for customers too.
- brucehoult 3y agoThe performance is about the same as the first Graviton servers in late 2018.
- Hamuko 3y agoDo they still offer ARM? I remember them killing the ARM bare metal back in the day.
- tempest_ 3y agoStill seem to offer ampere based vcpus https://labs.scaleway.com/en/amp2-instances/ https://labs.scaleway.com/en/amp2-instances/
- c0balt 3y agoThey are discontinued as of the end of January 2024. (See the FAQ section). Their only ARM appears to be Cost Optimized Arm: https://www.scaleway.com/en/cost-optimized-instances-based-on-arm/ https://www.scaleway.com/en/cost-optimized-instances-based-o...
- brucehoult 3y ago
- freeqaz 3y agoI couldn't find the value, but how much are they charging per month for these boxes? I see they have 4 CPU cores and 16gb of RAM.
- theanonymousone 3y agoDoes Docker work with RISC-V?
- cpswan 3y agoYes. I’ve been running it on a VisionFive 2 and a BeagleV-Ahead.
- pella 3y agohttps://hub.docker.com/u/riscv64 https://hub.docker.com/u/riscv64 minimal pre-build images ...
- brucehoult 3y agoIt absolutely does. I use it every day. You can run your RISC-V images transparently on your x86 or Arm (e.g. Apple) machines, as docker desktop automatically uses QEMU. Or run them natively in docker on your RISC-V board. Minimal starter image: riscv64/ubuntu
- b9b10eb736 3y agoI works great (with the usual requirement of having the expected kernel options/modules enabled). The main issue right now is the lack of image support for RISC-V. I hope this is going to change if hardware starts becoming accessible.
- fodkodrasz 3y ago100 Mbit/s NIC? Seems a bit thin.
- mistrial9 3y agogreat for code, terrible for lots of data. maybe not trendy but neither is it fatal?
- CuriousCosmic 3y agoFor 4 cores and 16GB of RAM? not really. That's probably close to saturation for the hardware for most workloads other than raw data streaming. The real sell of this hardware is that it's doing this with about 5W of power draw at peak utilisation.
- znpy 3y agoDoe these cpus have any cryptographic hardware acceleration? They list gpus and npus only. I have an old atom-based kimsufi by ovh, cryptography will eat almost a full core when doing file transfer over ssh or any kind of https… No cryptographic hardware acceleration could really be the Achilles’ tendon for this platform.
- Findecanor 3y agoThe T-Head C910: no. It is considered a bit of an old core by now. It is open source so it has been adopted a lot. The RISC-V standard has extensions for both scalar and vector cryptography instructions but yet only a few cores out there support one or the other. Look out for CPUs based on the SiFive P670 which should have the latter. When Android smartphones with RISC-V show up, they will also have vector cryptography.
- brucehoult 3y ago> T-Head C910: no. It is considered a bit of an old core by now Announced in July 2019, it is one of the most recent RISC-V cores you can buy. Hardware takes time, usually 3-4 years to go from announcement of a core to an SBC you can buy. The C910 is the only RISC-V core you can buy in an SoC with 64 of them (Milk-V Pioneer) The only newer core you can buy is the C908, available only in the K230 SoC on the CanMV-K230 board. It had some advantages (it's the only board rn with Vector 1.0), but it also has the HUGE disadvantages of being single core and only 0.5 GB RAM, vs quad core and 16 GB RAM on this cloud offering. > Look out for CPUs based on the SiFive P670 This is not available. The first boards are expected late this year. It will be a huge advance, certainly, with twice the speed per core, and the first SoC SG2380 with it having 16 cores. But not today.
- camel-cdr 3y agoI'll reiterate what I wrote before: 042€/hour per hour of compute is a great deal for developers. If you tests with cross compilation and qemu anyways and sometimes needs test/benchmark on the native hardware, then this means you can spend about 5€ and you are probably set for months if not a year. Also, with the latest gcc you can finally target rvv 0.7.1, which is supported by these CPUs. You just write your standardized rvv 1.0 intrinsics and if you add `-march=64gcxtheadvector` gcc 14 will just generate the equivalent rvv 0.7.1: https://godbolt.org/z/va9sfEnMW https://godbolt.org/z/va9sfEnMW
- justahuman74 3y agoWe probably want to encourage people to forget pre 1.0 vectors exists, to ease ecosystem fragmentation
- brucehoult 3y agoThat's what the SiFive mafia have been trying to get people to do, for the three years since Nezha arrived with RVV 0.7.1, while they (still!) have zero RVV hardware available for the end user to buy. It's pure FUD. The x86 world somehow survives with MMX, SSE, SSE2, SSE3, SSE4, AVX, AVX2, AVX512. The Arm word has a few incompatible variants too, with VFP, a couple of variations of NEON, SVE, SVE2, MVE. In comparison, RVV draft 0.7.1 and ratified 1.0 are practically the same thing. With GCC 14 transparently compiling unmodified code using RVV C intrinsics to either 0.7.1 or 1.0 there is very little cost or reason not to support both. RVV 0.7.1 is available in the vast majority of RISC-V SBCs in the world today, from the $5 Milk-V Duo (1.0 GHz C906, 64 MB RAM, 256M & 512M available for a few bucks more), to the ~$30 Lichee RV [dock] and MangoPi MQ Pro, to the $120-$180 Lichee Pi 4A, to the $2500 64 core Milk-V Pioneer. With the sole exception of the CanMV-K230 (single core, 0.5 GB RAM), if a RISC-V board on sale today doesn't have RVV 0.7.1 then it doesn't have vectors at all.
- kragen 3y agoi think the vast majority of risc-v sbcs in the world today don't support any v extension at all, yeah it's wonderful news that gcc is able to paper over the compatibility problems now
- ReflectedImage 3y agoCan we ditch virtual machines if we are packing 672 servers per rack?
- yjftsjthsd-h 3y agoThese aren't VMs?
- yubofr 3y ago[dead]
- ReflectedImage 3y agoOne of the main points of VMs is to subdivide servers. But if we packing low power servers this densely we might not need to.
- lewis1028282 3y agoWhat's the recommended way to learn RISC-V assembly (including SIMD)? For ARM I just found a book I liked and did the exercises on my Mac M1 (replacing system call numbers etc and changing page sizes).
- camel-cdr 3y agoEdit: sorry I missread, I though you were just interested in the vector extension (SIMD) for the genral assembly there isn't mutch to learn tbh, look at the isa reference card and maybe also look at the B (bit manipulation) extension: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/... --- Here are some resources on RVV I can recommend: RVV spec (also look at the examples in the repo): https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado... RVV intrinsics viewer: https://dzaima.github.io/intrinsics-viewer https://dzaima.github.io/intrinsics-viewer Tutorial: RISC-V Vector Extension Demystified (3 hour video going over every instruction): https://youtu.be/oTaOd8qr53U https://youtu.be/oTaOd8qr53U RISC-V Vector extension in a nutshell: https://fprox.substack.com/p/risc-v-vector-extension-in-a-nutshell-part-1 https://fprox.substack.com/p/risc-v-vector-extension-in-a-nu... If you want to see a more complex example/real world application, then you might also be interested in my article about vectorizing unicode conversions: https://camel-cdr.github.io/rvv-bench-results/articles/vector-utf.html https://camel-cdr.github.io/rvv-bench-results/articles/vecto... In terms of development I'd recommend using qemu and a cross compiler, or if you want hardware try to get the kendryte k230 (currently the only sbc with rvv 1.0 support) or wait a bit for better hardware (BPI-F3 and sg2380 should release this year).
- kragen 3y agoi'm probably not a good person to give advice on this, but what i've been doing is installing the cross-compilation gcc environment under debian and qemu-user. this allows me to build statically linked executables and run them as if they were native executables, and also to disassemble the executables and object files with riscv64-linux-gnu-objdump (though it produces incorrect output for instructions like addi and slli, it's good enough to see what's going on) specifically i installed gcc-riscv64-linux-gnu and qemu-user-binfmt also i read the risc-v spec and assembly programming manual i also got some risc-v single-board computers but haven't done anything with them yet i haven't been doing anything with the v extension, which i think is the most widely supported simd-like extension; though it's not exactly simd, it offers the same kinds of benefits for the same kinds of applications
- wut42 3y agoPreviously https://news.ycombinator.com/item?id=39548179 https://news.ycombinator.com/item?id=39548179
- kragen 3y agoprobably the things that will be most interesting to people: - SoC T-Head 1520 CPU (C910) RV64IMAFDCV0P7_Zicsr_Zifencei_Zfh_XTheadc 4 cores 1.85 GHz (though i think the v extension on the c910 is the pre-ratification 0.7.1 v extension; see https://news.ycombinator.com/item?id=39585519 https://news.ycombinator.com/item?id=39585519 for more detail) - 128 GB eMMC - Debian, Ubuntu, Alpine - between 0.96W and 1.9W per 1.8GHz core - €15.99/month or €0.042/hour
- deleted 3y ago[deleted]
- mise_en_place 3y agoThis looks interesting, I have been meaning to try RISC-V outside of an emulated environment. I have a visionfive board on my desk but gave up trying to figure out how to flash a production OS. There was some shady version of Fedora they offer but I prefer to flash my own via buildroot or yocto.
- Luctct 3y agoI wonder what payment methods they accept. On the site: no information. FAQ: "You can order your Elastic Metal RV1 server directly on the order page" click order page: -> "create an account to view the page" "I have a question, a problem, what can I do? Like all Scaleway services, you can contact us officially via our support center, or informally via the Scaleway Community Slack." click support center: -> "create an account to view the page" Scaleway Community Slack: -> "your browser is not sanctioned by our strikt kompliance kommitat" You know what, never mind.
- niij 3y agoCredit cards and SEPA at a minimum.
- k8svet 3y agoAnd they use Jumio. Instantly noped out after doing a number of other steps to get my account going. I have to verify bank deposits, and upload my ID through that piece of shit Jumio? The brilliant product built by people incapable of understanding that just letting me upload my gd damn ID is easier than trying to get me to complete the flow on my phone. No. No, actually there are plenty of people willing to take my money. Christ, it's far less of a hassle to get a crypto account opened on a decent exchange. I can't be the only one who just nopes out at stuff like this. This is on top of the unactionable banner I have that tells me I have a pending contract (I have no pending contract, and no reason I would have one). Okay Scaleway, I get it, I'll move on.
- seblu 3y agoWe added an FAQ question (https://labs.scaleway.com/en/em-rv1/#i-have-a-question https://labs.scaleway.com/en/em-rv1/#i-have-a-question) with a link to the Elastic Metal documentation where you can find the payment methods.
- rubatuga 3y ago> We are committed to providing you with the best possible experience, but please note that the artisanal design and the youth of RISC-V processor architectures do not allow us to guarantee a specific level of service, resulting in an SLA of 0%.
- jononor 3y agoGreat option to use as a CI server / job runner if one has a project targeting RISC-V. Of course one could use emulation or put a CI runner on some board in a closet somewhere. But cloud image is convenient, so it is nice to be able to do this now, just as on x86 and ARM.
- SergeAx 3y agoThese guys are unbelievable. They were the first to provide ARM servers (non-virtual, if I remember correctly), and now this. I hope they are benefitting from those innovations.