7 ms·

Filament – A Language for Fearless Hardware Design

87 points by nbrempel 3y ago

bb88 3y ago
I think this is super interesting. Kind of like a rust style language for symbolic logic. The timing aspect is super interesting, though I wonder if a compiler given an fpga and a program could optimize the hard parts on an fpga and run the rest on a risc V core.
speps 3y ago
Also: Filament is a real-time physically-based renderer written in C++. It is mobile-first, but also multi-platform. https://google.github.io/filament/ https://google.github.io/filament/
carterschonwald 3y ago
There’s some fun pl work in this project
j16sdiz 3y ago
I never really understand how HDL works. I meant, in software programming, we usually program by either specifying the sequence or dependency. In hardware, nothing runs sequentially, and signals propagate _with delay_. Everything happens at the same time, yet nothing run at the exact same moment. How could we express these chaos in for-loops and procedure look alikes?
- aappleby 3y ago
  For loops are one of those things that just don't really exist in hardware. The way I like to think of hardware is as a machine that takes a giant blob of state, applies a pure function to it, and when the clock goes from low to high it replaces the original state with the new one and the process starts again.
  - bsder 3y ago
    > For loops are one of those things that just don't really exist in hardware. Hardware for loops are just fine if you think of a for loop as existing in space rather than time--effectively it is always fully unrolled. > The way I like to think of hardware is as a machine that takes a giant blob of state, applies a pure function to it, and when the clock goes from low to high it replaces the original state with the new one and the process starts again. That's the way hardware guys think of it, too. :) https://en.wikipedia.org/wiki/Mealy_machine https://en.wikipedia.org/wiki/Mealy_machine
- CuriousCosmic 3y ago
  Preface: My experience is in verilog so I'll mostly be coming from there. In most HDLs you have two kinds of code, procedural and continuous code. Your continuous code is wires which propagate signals and continuous logic (basically pure functions). Since there aren't any registers in this logic, that means you generally need to do timing analysis to make sure it never gets too long between any two given registers (or latches if you are clock stealing). In verilog you mostly do this via assign statements and module instantiations. Your procedural code is register or latch based code. In verilog these are your always blocks. Here the code represents logic that occurs on every occurance of a given clock edge. The type of always block you use and which edge you specify changes exactly what happens but generally it means "this code runs during this interval every time the clock does a specific transition". Your inputs are generally going to be registers or latches and your outputs will be as well. Anything that happens must do so fast enough for the logic in between to reach a steady state and long enough for it to catch the edge of the register, edge of the edge triggered latch, or level of the level triggered latch and set the register or latch. If that sounds complicated it kinda is but generally you just let your timing analyzer figure it out and complain if stuff is too slow. Now outside your normal procedural code there are some other ones you see occasionally. There are also initial blocks which only run once and repeat blocks which only run a set number of times but with both you can pause or wait for a condition before proceeding. And there are also forever blocks. In all three of these blocks you can specify timings and delays for things. The most common use for forever blocks for example is to declare a clock that runs at a specified frequency. And initial blocks are used to do setup (such as start the clock loop, set initial values, etc). Now as to how you do loops and procedural logic? You use registers to break it up. That's what those always blocks are for. Your always block does a little bit of work each time and you use a state machine to codify where in the loop or procedural logic you are. In general FSMs (finite state machines) become your friend in HDL work very quickly.
  - pitaj 3y ago
    > continuous code > continuous logic This is terminology I'm used to. Generally this is called "combinational logic" in my experience. Is this a language or regional difference?
- pjc50 3y ago
  HDL when operating as an HDL doesn't convert things into for loops or procedures, it's specifying a configuration of gates or FPGA lookup tables. Crucially it doesn't contain any layout information, so additional phases of work are needed. There is some confusion because the hardware can also be simulated, in a fairly straightforward way - you just need to model all those delays and run an event based simulator. Then the existing HDLs like (System)Verilog contain actual programming language constructs that are just there for use in simulation and can't actually be replicated in hardware.
- rcxdude 3y ago
  The semantics of HDLs are generally kind of funky: they have a sequential interpretation, which us what simulators will use. That interpretation does involve a bunch of blocks which will operate in parallel, but within those blocks it's just a sequential series of operations not unlike aby other programming language. But HDLs generally can express a lot more than what can be automatically synthesised into hardware (this is useful because you often have simulation-only test blocks and harnesses which don't need to exist in hardware). The way you then write hardware is you define a series of blocks which are in the form "when this clock edge happens, update these variables in this way based on the previous value of variables in scope". It doesn't matter so much how you express this change, so long as the synthesis engine can map any given set of input variables to an output, which it will turn into digital logic. It is why verilog has odd constructs like "assign this value to this variable after the next time step". It's not unlike writing event-driven non-blocking code (without async or green threads). Note at this point that the HDL written is saying nothing about delays: by running it in simulation, everything will complete in time for the next clock cycle. And the synthesiser will happily produce a circuit which the place and router can't actually make fast enough for the next cycle. That's where two other parts come in: firstly there's timing analysis which takes the low-level results of the place-and-route and basically tries to work out the fastest and slowest a signal can pass from one register output to another register input, and how that compares to the clocks to those registers (usually it'll be the same clock). That is generally what will tell you if what you've written won't work in some situation or another. And secondly, the tool can also take that low-level compiler outout, and give you a kind of "decompiled" version in your HDL, which doesn't bear much resemblance to what you put in but does include all the estimated delays, so you can simulate (much more slowly) what the timings will actually look like. The upshot of which us that writing an HDL generally involves thinking about what the hardware would look like, writing some code that simulates what that hardware would be doing, running it through a slow build cycle, looking at what hardware was actually generated and working put why it's failing timing, thinking about how to change the hardware and then changing the code to get the sythesis tool to spit out the right version of that. You don't tend to get super high levels of abstraction in a given execution path: more the abstraction is in how you connect those parallel blocks together.
thrtythreeforty 3y ago
My experience with most "neo HDLs" is that they are all code generators which make the tedious part easy and don't really end up touching the hard part. This may be the first HDL I've seen that attempts to move the needle on catching bugs at compile time. (I've worked with several engineers, on hardware bugs which turned out to be pipelining errors, who did not understand what I meant by "make this design error inexpressible.") I have several pages of notes on what I'd do differently if I designed my own HDL - the typical software engineer hubris - and this is the first language I've seen that starts to line up with what I was thinking. Another perennial area where bugs crop up are when crossing clock and reset domains. The language ought to be able to make it so that you simply can't make many kinds of clock domain errors - trying to read a signal from the wrong clock domain shouldn't compile. Dedicated "unsafe" primitives from a stdlib should perform the crossing and the type conversion.
- FPGAhacker 3y ago
  Every time I see one of these pop up, the thought that software engineers are forever trying to avoid knowledge, understanding, and wisdom with another layer of abstraction comes to mind. I’m all in favor of a better HDL. Verizon/SystemVerilog is loaded with completely non-obvious landmines. I’ve been doing this so long I forget they are there, but it’s pretty painful seeing someone new to the language step on them. But the alternative, VHDL has largely fallen out of favor in the US. You would be hard pressed to find a more strongly typed language than VHDL, but damn is it verbose. None of the footguns, but you might get an RSA before you finish typing the code in. If you have ever given Ada a try, VHDL will look pretty familiar. I know this may be a weird thing for software folks to think about, but writing HDL is a tiny part of digital design. In digital design, if done with discipline, writing the HDL is an almost mechanical process of translating the design. In a design that might take a year, writing the code might be 3 weeks. Done without discipline you will spend all your time debugging. Wondering why it worked in the lab an hour ago, but after lunch nothing works and you won’t be able to make sense of it. Understanding basic combinational logic, then sequential logic, followed by state machines (which are the bread and butter of digital design), followed by understanding IO timing and timing constraints (a brain damaged “language” to itself) will take you far. Domain crossing isn’t so bad if you have those fundamentals. Then you can spend time learning algorithms other more interesting things. Writing low power software accelerators for neural nets and signal processing. You can go through all the gyrations of language design in the world, but the language isn’t the hard part. There is a huge amount of improvement to be done, no doubt. But digital design is not the language. If you want to make the world of digital design a better place, more open, easier to break into, work on tools, not languages. I’d give a kidney for an open source timing diagrammer that could do simple setup and hold checks, create derived signals through Boolean combinations of other signals, and emulate a flop. I’d do it, but I’ve tried and programming a gui is about the most painful thing I’ve done on a computer. So much work for so little payoff.
unwind 3y ago
Very cool. I was interested in the use of Filament to implement an entire RISC V processor ("frisc") but the link [1] at the bottom of the readme is broken and some quick searches of both Github and the web turned up nothing. Does anyone know what's up? [1]: https://github.com/cucapra/filament/tree/main/frisc https://github.com/cucapra/filament/tree/main/frisc
- hobofan 3y ago
  It's under /apps in the repo: https://github.com/cucapra/filament/tree/f5da227a059f181b9964e0ea4af077573c7a1cf8/apps/frisc https://github.com/cucapra/filament/tree/f5da227a059f181b996...
- deleted 3y ago
  [deleted]
gchadwick 3y ago
Whilst I'm often quite sceptical of new HDLs (see my other comment on this post) it is nice to see HDL and other silicon content pop up so often on HN. There's a lot of keen people doing interesting things here and it's great to see all the new developments.
irq-1 3y ago
html { font-weight: 100; } Can we please stop with illegible text? Color: 333 indeed.

87 points by nbrempel 3y ago

bb88 3y ago

I think this is super interesting. Kind of like a rust style language for symbolic logic. The timing aspect is super interesting, though I wonder if a compiler given an fpga and a program could optimize the hard parts on an fpga and run the rest on a risc V core.

speps 3y ago

Also: Filament is a real-time physically-based renderer written in C++. It is mobile-first, but also multi-platform. https://google.github.io/filament/ https://google.github.io/filament/

carterschonwald 3y ago

There’s some fun pl work in this project

j16sdiz 3y ago

I never really understand how HDL works. I meant, in software programming, we usually program by either specifying the sequence or dependency. In hardware, nothing runs sequentially, and signals propagate _with delay_. Everything happens at the same time, yet nothing run at the exact same moment. How could we express these chaos in for-loops and procedure look alikes?

aappleby 3y ago
For loops are one of those things that just don't really exist in hardware. The way I like to think of hardware is as a machine that takes a giant blob of state, applies a pure function to it, and when the clock goes from low to high it replaces the original state with the new one and the process starts again.
- bsder 3y ago
  > For loops are one of those things that just don't really exist in hardware. Hardware for loops are just fine if you think of a for loop as existing in space rather than time--effectively it is always fully unrolled. > The way I like to think of hardware is as a machine that takes a giant blob of state, applies a pure function to it, and when the clock goes from low to high it replaces the original state with the new one and the process starts again. That's the way hardware guys think of it, too. :) https://en.wikipedia.org/wiki/Mealy_machine https://en.wikipedia.org/wiki/Mealy_machine
CuriousCosmic 3y ago
Preface: My experience is in verilog so I'll mostly be coming from there. In most HDLs you have two kinds of code, procedural and continuous code. Your continuous code is wires which propagate signals and continuous logic (basically pure functions). Since there aren't any registers in this logic, that means you generally need to do timing analysis to make sure it never gets too long between any two given registers (or latches if you are clock stealing). In verilog you mostly do this via assign statements and module instantiations. Your procedural code is register or latch based code. In verilog these are your always blocks. Here the code represents logic that occurs on every occurance of a given clock edge. The type of always block you use and which edge you specify changes exactly what happens but generally it means "this code runs during this interval every time the clock does a specific transition". Your inputs are generally going to be registers or latches and your outputs will be as well. Anything that happens must do so fast enough for the logic in between to reach a steady state and long enough for it to catch the edge of the register, edge of the edge triggered latch, or level of the level triggered latch and set the register or latch. If that sounds complicated it kinda is but generally you just let your timing analyzer figure it out and complain if stuff is too slow. Now outside your normal procedural code there are some other ones you see occasionally. There are also initial blocks which only run once and repeat blocks which only run a set number of times but with both you can pause or wait for a condition before proceeding. And there are also forever blocks. In all three of these blocks you can specify timings and delays for things. The most common use for forever blocks for example is to declare a clock that runs at a specified frequency. And initial blocks are used to do setup (such as start the clock loop, set initial values, etc). Now as to how you do loops and procedural logic? You use registers to break it up. That's what those always blocks are for. Your always block does a little bit of work each time and you use a state machine to codify where in the loop or procedural logic you are. In general FSMs (finite state machines) become your friend in HDL work very quickly.
- pitaj 3y ago
  > continuous code > continuous logic This is terminology I'm used to. Generally this is called "combinational logic" in my experience. Is this a language or regional difference?
pjc50 3y ago
HDL when operating as an HDL doesn't convert things into for loops or procedures, it's specifying a configuration of gates or FPGA lookup tables. Crucially it doesn't contain any layout information, so additional phases of work are needed. There is some confusion because the hardware can also be simulated, in a fairly straightforward way - you just need to model all those delays and run an event based simulator. Then the existing HDLs like (System)Verilog contain actual programming language constructs that are just there for use in simulation and can't actually be replicated in hardware.
rcxdude 3y ago
The semantics of HDLs are generally kind of funky: they have a sequential interpretation, which us what simulators will use. That interpretation does involve a bunch of blocks which will operate in parallel, but within those blocks it's just a sequential series of operations not unlike aby other programming language. But HDLs generally can express a lot more than what can be automatically synthesised into hardware (this is useful because you often have simulation-only test blocks and harnesses which don't need to exist in hardware). The way you then write hardware is you define a series of blocks which are in the form "when this clock edge happens, update these variables in this way based on the previous value of variables in scope". It doesn't matter so much how you express this change, so long as the synthesis engine can map any given set of input variables to an output, which it will turn into digital logic. It is why verilog has odd constructs like "assign this value to this variable after the next time step". It's not unlike writing event-driven non-blocking code (without async or green threads). Note at this point that the HDL written is saying nothing about delays: by running it in simulation, everything will complete in time for the next clock cycle. And the synthesiser will happily produce a circuit which the place and router can't actually make fast enough for the next cycle. That's where two other parts come in: firstly there's timing analysis which takes the low-level results of the place-and-route and basically tries to work out the fastest and slowest a signal can pass from one register output to another register input, and how that compares to the clocks to those registers (usually it'll be the same clock). That is generally what will tell you if what you've written won't work in some situation or another. And secondly, the tool can also take that low-level compiler outout, and give you a kind of "decompiled" version in your HDL, which doesn't bear much resemblance to what you put in but does include all the estimated delays, so you can simulate (much more slowly) what the timings will actually look like. The upshot of which us that writing an HDL generally involves thinking about what the hardware would look like, writing some code that simulates what that hardware would be doing, running it through a slow build cycle, looking at what hardware was actually generated and working put why it's failing timing, thinking about how to change the hardware and then changing the code to get the sythesis tool to spit out the right version of that. You don't tend to get super high levels of abstraction in a given execution path: more the abstraction is in how you connect those parallel blocks together.

thrtythreeforty 3y ago

My experience with most "neo HDLs" is that they are all code generators which make the tedious part easy and don't really end up touching the hard part. This may be the first HDL I've seen that attempts to move the needle on catching bugs at compile time. (I've worked with several engineers, on hardware bugs which turned out to be pipelining errors, who did not understand what I meant by "make this design error inexpressible.") I have several pages of notes on what I'd do differently if I designed my own HDL - the typical software engineer hubris - and this is the first language I've seen that starts to line up with what I was thinking. Another perennial area where bugs crop up are when crossing clock and reset domains. The language ought to be able to make it so that you simply can't make many kinds of clock domain errors - trying to read a signal from the wrong clock domain shouldn't compile. Dedicated "unsafe" primitives from a stdlib should perform the crossing and the type conversion.

FPGAhacker 3y ago
Every time I see one of these pop up, the thought that software engineers are forever trying to avoid knowledge, understanding, and wisdom with another layer of abstraction comes to mind. I’m all in favor of a better HDL. Verizon/SystemVerilog is loaded with completely non-obvious landmines. I’ve been doing this so long I forget they are there, but it’s pretty painful seeing someone new to the language step on them. But the alternative, VHDL has largely fallen out of favor in the US. You would be hard pressed to find a more strongly typed language than VHDL, but damn is it verbose. None of the footguns, but you might get an RSA before you finish typing the code in. If you have ever given Ada a try, VHDL will look pretty familiar. I know this may be a weird thing for software folks to think about, but writing HDL is a tiny part of digital design. In digital design, if done with discipline, writing the HDL is an almost mechanical process of translating the design. In a design that might take a year, writing the code might be 3 weeks. Done without discipline you will spend all your time debugging. Wondering why it worked in the lab an hour ago, but after lunch nothing works and you won’t be able to make sense of it. Understanding basic combinational logic, then sequential logic, followed by state machines (which are the bread and butter of digital design), followed by understanding IO timing and timing constraints (a brain damaged “language” to itself) will take you far. Domain crossing isn’t so bad if you have those fundamentals. Then you can spend time learning algorithms other more interesting things. Writing low power software accelerators for neural nets and signal processing. You can go through all the gyrations of language design in the world, but the language isn’t the hard part. There is a huge amount of improvement to be done, no doubt. But digital design is not the language. If you want to make the world of digital design a better place, more open, easier to break into, work on tools, not languages. I’d give a kidney for an open source timing diagrammer that could do simple setup and hold checks, create derived signals through Boolean combinations of other signals, and emulate a flop. I’d do it, but I’ve tried and programming a gui is about the most painful thing I’ve done on a computer. So much work for so little payoff.

unwind 3y ago

Very cool. I was interested in the use of Filament to implement an entire RISC V processor ("frisc") but the link [1] at the bottom of the readme is broken and some quick searches of both Github and the web turned up nothing. Does anyone know what's up? [1]: https://github.com/cucapra/filament/tree/main/frisc https://github.com/cucapra/filament/tree/main/frisc

hobofan 3y ago
It's under /apps in the repo: https://github.com/cucapra/filament/tree/f5da227a059f181b9964e0ea4af077573c7a1cf8/apps/frisc https://github.com/cucapra/filament/tree/f5da227a059f181b996...
deleted 3y ago
[deleted]

gchadwick 3y ago

Whilst I'm often quite sceptical of new HDLs (see my other comment on this post) it is nice to see HDL and other silicon content pop up so often on HN. There's a lot of keen people doing interesting things here and it's great to see all the new developments.

irq-1 3y ago

html { font-weight: 100; } Can we please stop with illegible text? Color: 333 indeed.