In principle 7nm has 57, 64 or 76nm gate pitch. Routing is quite inefficient in 57nm gate pitch, so 64nm is used most often. As far as I can see in the design r

In principle 7nm has 57, 64 or 76nm gate pitch. Routing is quite inefficient in 57nm gate pitch, so 64nm is used most often. As far as I can see in the design rule manual there's no possibility for 60nm pitch. 40nm metal pitch for colored metals is correct. Standard cell height pitch has a similar story, 270nm height is possible but means high parasitics induced RC delay. For good performance 300nm or higher height pitches are used. These tables miss a huge context though. TSMC N7 drawn gate length is like 20nm, not 60nm. This pitch includes diffusion (source/drain) and contacts. Biggest limit is interconnect (vias are impossible to shrink as we make them now).