3 ms·
Nit: x86 has acquire/release and seq_cst for load/stores (it technically also has relaxed, but it is not useful to map it to c++11 relaxed). What x86 lacks is w
by gpderetta 3y ago
Nit: x86 has acquire/release and seq_cst for load/stores (it technically also has relaxed, but it is not useful to map it to c++11 relaxed). What x86 lacks is weaker ordering for RMW, but there are a lot of useful lock free algorithms that are implementable just or mostly with load and stores and it can be a significant win to use non-seq-cst stores for this on x86
- haberman 3y agoIndeed there is different code generated by seq_cst for stores. Though for loads it appears to be the same: https://godbolt.org/z/WbvEcM83q https://godbolt.org/z/WbvEcM83q
- gpderetta 3y agoYes, seqcst loads map to plain loads on x86.
- loeg 3y agoRe: the godbolt example, note that release semantics are not meaningful for load operations. > If order is one of std::memory_order_release and std::memory_order_acq_rel, the behavior is undefined. https://en.cppreference.com/w/cpp/atomic/atomic/load https://en.cppreference.com/w/cpp/atomic/atomic/load
- vlovich123 3y agoI would have to imagine you mean x86-64 right? I would imagine 32bit x86 doesn’t have those instructions? I’m also kind of curious if a lot of modern code compiled to x86 would see consistency issues running on old CPUs before TSO was formalized (like a p2 multiprocessor server).
- loeg 3y ago32-bit x86 has many of the same instructions, including cmpxchg8b (in models dating to the 90s).