3 ms·

I didn't notice this was the table since you didn't attribute the source and it wasn't spaced visually. A table on https://en.wikipedia.org/wiki/2_nm_process h

I didn't notice this was the table since you didn't attribute the source and it wasn't spaced visually. A table on https://en.wikipedia.org/wiki/2_nm_process https://en.wikipedia.org/wiki/2_nm_process suggests: '20 angstrom (Intel)' ~= 2 nanometer (industry) Process Gate Metal Year 7 nm 60 nm 40 nm 2018 5 nm 51 nm 30 nm 2020 3 nm 48 nm 24 nm 2022 2 nm 45 nm 20 nm 2024 1 nm 42 nm 16 nm 2026 However note that the feature size barely shrinks between 2 nm and 1nm. I'm not sure what size Intel will go with, but offhand this might be close to the limits of silicon as we know it. I'm not sure where things will get pushed in the quest for further progression. Also of note, IIRC some of AMD's presentations around when Ryzen launched involved mention that cache / memory (and maybe some other features?) on CPUs weren't scaling down effectively past 7 ~ 5 nm, which is one of the reasons GPUs had the cores and then external memory controllers. I know automakers and a bunch of other consumers that would like bulk (cheap) products made on modern wafers (300mm) with a semi-modern process that's super inexpensive. Particularly power ICs which would prefer lower leakage even if it means a slower response.

bippingchip 3y ago
These gate and metal pitch numbers don’t tell the whole story. In the end it’s logic gate density that counts. And while decreasing the gate and metal pitch, also the logic gates have shrunk to be smaller (typically expressed by measuring the height of a gate in amount of metal tracks) from 9tracks down to 6tracks. Changing the transistor from planar to fins, and now hopefully to ribbons with eventually stacked pmos and nmos are a big enabler. That said, we’re still not hitting the ideal scaling numbers. We’re just doing somewhat better than what’s suggested by poly and metal pitch only.

bippingchip 3y ago

These gate and metal pitch numbers don’t tell the whole story. In the end it’s logic gate density that counts. And while decreasing the gate and metal pitch, also the logic gates have shrunk to be smaller (typically expressed by measuring the height of a gate in amount of metal tracks) from 9tracks down to 6tracks. Changing the transistor from planar to fins, and now hopefully to ribbons with eventually stacked pmos and nmos are a big enabler. That said, we’re still not hitting the ideal scaling numbers. We’re just doing somewhat better than what’s suggested by poly and metal pitch only.