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Why aren't these companies investing more into 3-dimensional chips instead of trying to squeeze more on the same 2-dimensional die when we're so close to hard a

• peterfirefly 3y ago
  Cooling and power supply. Plus it's really hard to have more than one transistor level: you can try to put transistors on both sides of a die or you can take separate dies, grind some of them really thin, and then put them on top of each other.
• jsjohnst 3y ago
  I’m not the one who downvoted you, but while stacking in 3D might work for things like ram and storage, it doesn’t help the same way with cpu. They aren’t trying to get the overall die size smaller per se, but rather the node size. Generally speaking, smaller transistors = lower energy consumption + higher performance for the same number of transistors.
  • patmorgan23 3y ago
    I wonder how practical it would be to switch to non-binary transistors. I believe some early vacuum tubes where trinary instead of binary. Probably not practical but would be interesting to see how it could fit together.
    • wtallis 3y ago
      Storage (NAND flash) and many off-chip communication protocols (both wired and wireless) are already non-binary and use multiple discrete voltage levels. There's also a lot of interest in more or less analog storage and compute elements for ML, where it's fine to have weights and activations represented in a fundamentally fuzzy manner. But I don't think there's any promising way to perform discrete deterministic logic and computation in base 3 or higher using transistors, aside from what we already do for multi-bit quantities.
• tester756 3y ago
  They go into 3D Transistor stacking
• IncreasePosts 3y ago
  Heat dissipation is a huge issue for 3d designs, especially when you get deep in the z direction and not just a few levels.
  • Solvency 3y ago
    Ok so why not a hollow triangle? It doesn't have to be a cube.
    • wtallis 3y ago
      How would manufacturing a hollow triangular prism, or a cube, be accomplished more cheaply than assembling planar components? When people discuss the possibility of 3D semiconductor fabrication, they're usually talking about additive manufacturing of multiple layers of transistors atop a single silicon wafer substrate. That's only going to be economical if most of the volume deposited is used for transistors rather than needing to be removed later. Large hollow shapes would be difficult and wasteful to manufacture that way; transistors aren't as easy to 3d-print as plastic filament.
      • mjevans 3y ago
        I can't imagine it myself, though a massively parallel thing that didn't need to worry about heat might work. IDK is that what an optical type chip is supposed to somehow do? I know a little more about how semiconductors work; the heat parts are related to the waste energy from the transistors change between conducting and not. Since the semi-conduction parts need the conduction paths opened or closed by changing charge levels in the narrow parts. I can barely imagine some sort of interference based optical chip might not generate heat at the logic combination part, but something some-where's gotta flip/flop and that's probably where the heat will exist. The other option we've heard about for decades involves better conduction of the heat out of the chip. If that's the case thermally conductive layers could sandwich between stacked 2D layers. Maybe that'll finally be economically viable for high density logic. As far as RAM stacking seems to work well enough so far.
      • Solvency 3y ago