5 ms·

I don't know for Intel, but for TSMC the marketing numbers work like this: Marketing, Gate pitch, Metal Pitch, Year 7nm, 60nm, 40nm, 2018 5nm, 51nm, 30nm, 20

I don't know for Intel, but for TSMC the marketing numbers work like this: Marketing, Gate pitch, Metal Pitch, Year 7nm, 60nm, 40nm, 2018 5nm, 51nm, 30nm, 2020 3nm, 48nm, 24nm, 2022 2nm, 45nm, 20nm, 2024 1nm, 42nm, 16nm, 2026

layer8 3y ago
I wonder how they came up with the “1.4 nm” designation (which confusingly TSMC calls A14 now and Intel 14A).
culopatin 3y ago
Is there anything in the process that’s 7-1nm?
- CuriousCosmic 3y ago
  Nope. Quote: https://en.wikipedia.org/wiki/7_nm_process https://en.wikipedia.org/wiki/7_nm_process > The phrase "7 nm" does not refer to any dimension on the integrated circuits, and has no relation to gate length, metal pitch, or gate pitch; since at least 1997, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to physical properties. However, the smallest dimension within an individual transistor, the fin width, can sometimes be 7 nm. TSMC and Samsung's "10 nm" (10 LPE) processes are somewhere between Intel's "14 nm" and "10 nm" processes in transistor density.
  - deleted 3y ago
    [deleted]
ReptileMan 3y ago
Well what is 1nm measuring? The diameter of the sphere in which the combined gray brain matter of the marketing department could be squeezed into? Lithography wavelength?
- CuriousCosmic 3y ago
  It's a standardised "process" sizing established by the International Technology Roadmap for Semiconductors. Originally they did correspond to actual feature sizes but since around 1997, they no longer correlate to actual sizes and are more just a marketing term that matches the same naming scheme as previously. Occassionally a given process will correspond to actual sizes but it's more out of luck than anything else.
  - bgnn 3y ago
    This isn't fully correct. Drawn 7nm is like 20nm, but effective gate length is shorter due to short channel effects. So, this numbers are almost 1-to-1 reflection of effective gate length. People mix up the transistor pitch with gate length. We can make small gate length devices but diffusion (source/drain) and contacts don't shrink as much, so we end up having a larger area needed for these.
- deleted 3y ago
  [deleted]
- mappu 3y ago
  1nm is the real physical size of a transistor that you would need, to get equivalent performance characteristics, if the transistor's other layout characteristics were fixed in 1997. The divergence is because when FinFET layout was introduced, it gave as much of as improvement as a node shrink would have otherwise done. See also: AMD Athlon "3000" CPUs, clocked at only 2.x GHz, performing "as well as an equivalent" 3.0GHz Intel CPU,
tromp 3y ago
The step from 7 to 5nm shrunk pitch to 85%, a mere 19% of marketing hype. But the step from 2 to 1nm shrunk gate pitch to 93.3% instead of the suggested 50%, a large 87% marketing hype. Or viewed as a shrink by only 6.7%, it's a whopping 600+% hype.
- mrandish 3y ago
  The hype-to-reality gap is going to keep getting much bigger every generation of announcements due to Dennard scaling and the end of Moore's Law. I was fortunate enough to be an active computer technologist through the "golden age" from 1980 to ~2010. Every three to four years things got about twice as fast for around half the cost. And not just some features or aspects but almost the entire system in almost every way. We had no idea back then just how extraordinary that period was. Today, the industry has regressed to hyping tiny incremental gains in narrow sub-metrics which only rarely have a material impact on overall performance across an entire system or most applications and usually at higher cost. Those that entered the industry in the last 15 years don't really appreciate just how much progress has slowed to a crawl. Sadly, looking at the ten year roadmap projections from the likes of IMEC, there aren't any big leaps on the horizon. Progress will come mostly in single-digit percentages and most gains will be increasingly conditional (eg limited to one logic type or only in certain contexts). And the costs are going to keep skyrocketing. I hope we'll "get lucky" with some unexpected breakthrough but there's no reason to expect that.
  - hinkley 3y ago
    “We” knew the entire time. Nobody had to listen because the lunches were still free.
  - davidgay 3y ago
    > And not just some features or aspects but almost the entire system in almost every way. Except latency. RAM (uncached) latency managed maybe 3x (250ns in the 80s to sub-100ns these days)? The only really significant latency improvement is spinning-disks to SSD.
  - aurareturn 3y ago
Mistletoe 3y ago
This is such a ridiculous way to do, well anything. Especially something that’s supposed to be based on technology and science. It’s how you would sell infomercial products or gas station virility pills.
- Analemma_ 3y ago
  It's true that marketing sort of ran away with it but it's important to note that the original idea was sound and didn't have to do with marketing hype. "Process shrinks" require many different industries to coordinate or else nothing can get done, and the ITRS roadmap was meant to be the mechanism to accomplish that coordination. What happened was that not long after it was introduced the actual feature sizes diverged from the names on the roadmap, but they decided to just keep using the roadmap names because the need for coordination didn't actually go away and, well, the names were right there, why bother changing them. The end result seems crazy now but it's the result a set of decisions that were individually rational, not marketing-driven, at each step.
  - coffeebeqn 3y ago
    They got their work cut out for them for the <1nm naming scheme. 900pm?
    - buu700 3y ago
      Seems straightforward to me. 0nm, -1nm, -2nm, etc.
      - fasa99 3y ago
        It's fine, there's a roadmap for it - "the 1000 quark" node should last as a good 10, 15 years until we get to "1 quark" Then we move onto the "10,000 planck length node". That should easily get us to the end of Moore's law.
Lance_ET_Compte 3y ago
How many atoms thick is the gate oxide on a 1nm process?
mjevans 3y ago
I didn't notice this was the table since you didn't attribute the source and it wasn't spaced visually. A table on https://en.wikipedia.org/wiki/2_nm_process https://en.wikipedia.org/wiki/2_nm_process suggests: '20 angstrom (Intel)' ~= 2 nanometer (industry) Process Gate Metal Year 7 nm 60 nm 40 nm 2018 5 nm 51 nm 30 nm 2020 3 nm 48 nm 24 nm 2022 2 nm 45 nm 20 nm 2024 1 nm 42 nm 16 nm 2026 However note that the feature size barely shrinks between 2 nm and 1nm. I'm not sure what size Intel will go with, but offhand this might be close to the limits of silicon as we know it. I'm not sure where things will get pushed in the quest for further progression. Also of note, IIRC some of AMD's presentations around when Ryzen launched involved mention that cache / memory (and maybe some other features?) on CPUs weren't scaling down effectively past 7 ~ 5 nm, which is one of the reasons GPUs had the cores and then external memory controllers. I know automakers and a bunch of other consumers that would like bulk (cheap) products made on modern wafers (300mm) with a semi-modern process that's super inexpensive. Particularly power ICs which would prefer lower leakage even if it means a slower response.
- bippingchip 3y ago
  These gate and metal pitch numbers don’t tell the whole story. In the end it’s logic gate density that counts. And while decreasing the gate and metal pitch, also the logic gates have shrunk to be smaller (typically expressed by measuring the height of a gate in amount of metal tracks) from 9tracks down to 6tracks. Changing the transistor from planar to fins, and now hopefully to ribbons with eventually stacked pmos and nmos are a big enabler. That said, we’re still not hitting the ideal scaling numbers. We’re just doing somewhat better than what’s suggested by poly and metal pitch only.
lacker 3y ago
They should just call it "1 mn" where mn stands for "marketing nanometer"
bgnn 3y ago
In principle 7nm has 57, 64 or 76nm gate pitch. Routing is quite inefficient in 57nm gate pitch, so 64nm is used most often. As far as I can see in the design rule manual there's no possibility for 60nm pitch. 40nm metal pitch for colored metals is correct. Standard cell height pitch has a similar story, 270nm height is possible but means high parasitics induced RC delay. For good performance 300nm or higher height pitches are used. These tables miss a huge context though. TSMC N7 drawn gate length is like 20nm, not 60nm. This pitch includes diffusion (source/drain) and contacts. Biggest limit is interconnect (vias are impossible to shrink as we make them now).

layer8 3y ago

I wonder how they came up with the “1.4 nm” designation (which confusingly TSMC calls A14 now and Intel 14A).

culopatin 3y ago

Is there anything in the process that’s 7-1nm?

CuriousCosmic 3y ago
Nope. Quote: https://en.wikipedia.org/wiki/7_nm_process https://en.wikipedia.org/wiki/7_nm_process > The phrase "7 nm" does not refer to any dimension on the integrated circuits, and has no relation to gate length, metal pitch, or gate pitch; since at least 1997, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to physical properties. However, the smallest dimension within an individual transistor, the fin width, can sometimes be 7 nm. TSMC and Samsung's "10 nm" (10 LPE) processes are somewhere between Intel's "14 nm" and "10 nm" processes in transistor density.
- deleted 3y ago
  [deleted]

ReptileMan 3y ago

Well what is 1nm measuring? The diameter of the sphere in which the combined gray brain matter of the marketing department could be squeezed into? Lithography wavelength?

CuriousCosmic 3y ago
It's a standardised "process" sizing established by the International Technology Roadmap for Semiconductors. Originally they did correspond to actual feature sizes but since around 1997, they no longer correlate to actual sizes and are more just a marketing term that matches the same naming scheme as previously. Occassionally a given process will correspond to actual sizes but it's more out of luck than anything else.
- bgnn 3y ago
  This isn't fully correct. Drawn 7nm is like 20nm, but effective gate length is shorter due to short channel effects. So, this numbers are almost 1-to-1 reflection of effective gate length. People mix up the transistor pitch with gate length. We can make small gate length devices but diffusion (source/drain) and contacts don't shrink as much, so we end up having a larger area needed for these.
deleted 3y ago
[deleted]
mappu 3y ago
1nm is the real physical size of a transistor that you would need, to get equivalent performance characteristics, if the transistor's other layout characteristics were fixed in 1997. The divergence is because when FinFET layout was introduced, it gave as much of as improvement as a node shrink would have otherwise done. See also: AMD Athlon "3000" CPUs, clocked at only 2.x GHz, performing "as well as an equivalent" 3.0GHz Intel CPU,

tromp 3y ago

The step from 7 to 5nm shrunk pitch to 85%, a mere 19% of marketing hype. But the step from 2 to 1nm shrunk gate pitch to 93.3% instead of the suggested 50%, a large 87% marketing hype. Or viewed as a shrink by only 6.7%, it's a whopping 600+% hype.

mrandish 3y ago
The hype-to-reality gap is going to keep getting much bigger every generation of announcements due to Dennard scaling and the end of Moore's Law. I was fortunate enough to be an active computer technologist through the "golden age" from 1980 to ~2010. Every three to four years things got about twice as fast for around half the cost. And not just some features or aspects but almost the entire system in almost every way. We had no idea back then just how extraordinary that period was. Today, the industry has regressed to hyping tiny incremental gains in narrow sub-metrics which only rarely have a material impact on overall performance across an entire system or most applications and usually at higher cost. Those that entered the industry in the last 15 years don't really appreciate just how much progress has slowed to a crawl. Sadly, looking at the ten year roadmap projections from the likes of IMEC, there aren't any big leaps on the horizon. Progress will come mostly in single-digit percentages and most gains will be increasingly conditional (eg limited to one logic type or only in certain contexts). And the costs are going to keep skyrocketing. I hope we'll "get lucky" with some unexpected breakthrough but there's no reason to expect that.
- hinkley 3y ago
  “We” knew the entire time. Nobody had to listen because the lunches were still free.
- davidgay 3y ago
  > And not just some features or aspects but almost the entire system in almost every way. Except latency. RAM (uncached) latency managed maybe 3x (250ns in the 80s to sub-100ns these days)? The only really significant latency improvement is spinning-disks to SSD.
- aurareturn 3y ago

Mistletoe 3y ago

This is such a ridiculous way to do, well anything. Especially something that’s supposed to be based on technology and science. It’s how you would sell infomercial products or gas station virility pills.

Analemma_ 3y ago
It's true that marketing sort of ran away with it but it's important to note that the original idea was sound and didn't have to do with marketing hype. "Process shrinks" require many different industries to coordinate or else nothing can get done, and the ITRS roadmap was meant to be the mechanism to accomplish that coordination. What happened was that not long after it was introduced the actual feature sizes diverged from the names on the roadmap, but they decided to just keep using the roadmap names because the need for coordination didn't actually go away and, well, the names were right there, why bother changing them. The end result seems crazy now but it's the result a set of decisions that were individually rational, not marketing-driven, at each step.
- coffeebeqn 3y ago
  They got their work cut out for them for the <1nm naming scheme. 900pm?
  - buu700 3y ago
    Seems straightforward to me. 0nm, -1nm, -2nm, etc.
    - fasa99 3y ago
      It's fine, there's a roadmap for it - "the 1000 quark" node should last as a good 10, 15 years until we get to "1 quark" Then we move onto the "10,000 planck length node". That should easily get us to the end of Moore's law.

Lance_ET_Compte 3y ago

How many atoms thick is the gate oxide on a 1nm process?

mjevans 3y ago

I didn't notice this was the table since you didn't attribute the source and it wasn't spaced visually. A table on https://en.wikipedia.org/wiki/2_nm_process https://en.wikipedia.org/wiki/2_nm_process suggests: '20 angstrom (Intel)' ~= 2 nanometer (industry) Process Gate Metal Year 7 nm 60 nm 40 nm 2018 5 nm 51 nm 30 nm 2020 3 nm 48 nm 24 nm 2022 2 nm 45 nm 20 nm 2024 1 nm 42 nm 16 nm 2026 However note that the feature size barely shrinks between 2 nm and 1nm. I'm not sure what size Intel will go with, but offhand this might be close to the limits of silicon as we know it. I'm not sure where things will get pushed in the quest for further progression. Also of note, IIRC some of AMD's presentations around when Ryzen launched involved mention that cache / memory (and maybe some other features?) on CPUs weren't scaling down effectively past 7 ~ 5 nm, which is one of the reasons GPUs had the cores and then external memory controllers. I know automakers and a bunch of other consumers that would like bulk (cheap) products made on modern wafers (300mm) with a semi-modern process that's super inexpensive. Particularly power ICs which would prefer lower leakage even if it means a slower response.

bippingchip 3y ago
These gate and metal pitch numbers don’t tell the whole story. In the end it’s logic gate density that counts. And while decreasing the gate and metal pitch, also the logic gates have shrunk to be smaller (typically expressed by measuring the height of a gate in amount of metal tracks) from 9tracks down to 6tracks. Changing the transistor from planar to fins, and now hopefully to ribbons with eventually stacked pmos and nmos are a big enabler. That said, we’re still not hitting the ideal scaling numbers. We’re just doing somewhat better than what’s suggested by poly and metal pitch only.

lacker 3y ago

They should just call it "1 mn" where mn stands for "marketing nanometer"

bgnn 3y ago

In principle 7nm has 57, 64 or 76nm gate pitch. Routing is quite inefficient in 57nm gate pitch, so 64nm is used most often. As far as I can see in the design rule manual there's no possibility for 60nm pitch. 40nm metal pitch for colored metals is correct. Standard cell height pitch has a similar story, 270nm height is possible but means high parasitics induced RC delay. For good performance 300nm or higher height pitches are used. These tables miss a huge context though. TSMC N7 drawn gate length is like 20nm, not 60nm. This pitch includes diffusion (source/drain) and contacts. Biggest limit is interconnect (vias are impossible to shrink as we make them now).