This is really old news and sadly there wasn't anything new in this article, the issue remains. IBM [used to?] use eDRAM for their last-level caches which is a

This is really old news and sadly there wasn't anything new in this article, the issue remains. IBM [used to?] use eDRAM for their last-level caches which is a classic latency/capacity trade-off that seems reasonable. There are some amusing typos, like "single-core"/"dual-core" where they meant port rather than core.