To be pedantic because its fun: The random access Latency for L1 is indeed ~4 cycles, but RAM is more like 70ns+ (so you are .5 order of magnitude off, how dar

To be pedantic because its fun: The random access Latency for L1 is indeed ~4 cycles, but RAM is more like 70ns+ (so you are .5 order of magnitude off, how dare you?). These are my notes from an Anandtech article: RAM: 5950x: 79 ns (400 cycles) 3950x: 86 ns (400 cycles) 10900k: 71 ns Apple M1: 97 ns Apple M1 Max: 111 ns Apple A15P: 105 ns Apple A15E: 141 ns Apple A14P: 101 ns Apple A14E: 201 ns 888 X1: 114 ns L1 Cache: 5950x: 4 cycles (0.8 ns @ 5 GHz) Apple M1: 3 cycles Apple M1 Max: 3 cycles