4 ms·
Tip of the ice-berg. DRAM needs to be refreshed every X cycles. This means you don't know the time it takes to read from memory. You could be reading at a ref
by frozenport 3y ago
Tip of the ice-berg.
DRAM needs to be refreshed every X cycles.
This means you don't know the time it takes to read from memory. You could be reading at a refresh cycle. This circuitry also adds latency.
- LtdJorge 3y agoOP says SRAM, which doesn't decay so no refreshing.
- ndjdbdjdbev 3y agoTiming can simply mean the FETs that make up the logic circuits of a chip. The transition from high to low and low to high has a minimum safe time to register properly...