You can find out about the chip to chip interconnect from our paper below, section 2.3. I don't think that's custom. We achieve low latency by basically being

You can find out about the chip to chip interconnect from our paper below, section 2.3. I don't think that's custom. We achieve low latency by basically being a software-defined architecture. Our functional units operate completely orthoganal to each other. We don't have to batch in order to achieve parallelism and the system behaviour is completely deterministic, so we can schedule all operations precisely. https://wow.groq.com/wp-content/uploads/2023/05/GroqISCAPaper2022_ASoftwareDefinedTensorStreamingMultiprocessorForLargeScaleMachineLearning-1.pdf https://wow.groq.com/wp-content/uploads/2023/05/GroqISCAPape...