> AFAIK there's a performance hit using external ECC, as it adds an extra cycle. This may be the case in some specific implementations but nothing in the DDR5

> AFAIK there's a performance hit using external ECC, as it adds an extra cycle. This may be the case in some specific implementations but nothing in the DDR5 spec prevents you from pipelining the ECC calculations alongside the cycles you already need for cache management anyway. The memory itself and the interface don't care, they just do 72bit instead of 64bit.