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High-Bandwidth Memory (HBM) Architecture CPU Revolutionizes HPC (2022) [pdf]

1 points by peter_d_sherman 3y ago

peter_d_sherman 3y ago
>"The Xeon Max CPU can be used in three memory configurations: HBM only: In HBM-only mode, an HPC workload runs within 64 GB of package memory. The workload is bootable from HBM, and no code changes are required. Additionally, no external DDR5 memory is required. HBM cache: In cache mode, HBM functions as a memory-side cache for contents of DDR memory. In this mode, HBM is transparent to all software because the HBM cache is managed by hardware memory controllers. No code changes are required. HBM flat: In flat mode, both DDR and the HBM address spaces are visible to software. On a socket, each address space is exposed as a separate NUMA node. This mode requires software optimization." Related: https://www.intel.com/content/www/us/en/products/details/processors/xeon/max-series.html https://www.intel.com/content/www/us/en/products/details/pro...