3 ms·

Apple does not optimize for IPC. Apple has just designed the CPU cores with the highest IPC among all known until now. The highest IPC is the best choice for

Apple does not optimize for IPC. Apple has just designed the CPU cores with the highest IPC among all known until now. The highest IPC is the best choice for minimum energy consumption in a CPU with few cores, like a mobile phone or light laptop CPU, because it allows the same performance at a lower clock frequency. A higher IPC requires more transistors and more money spent for the design of the core. Apple has been rich enough to afford both the design cost and the cost of being able to use exclusively more advanced manufacturing processes. When the IPC is increased to very high values, the area and the power consumption are increased by greater factors than the increase in performance. Therefore, for a CPU with many cores, like a server CPU, the highest IPC is not the best. There will be a lower IPC that is better, because it allows packing more cores in a given chip area and a given thermal design power, leading to a higher aggregate performance for multi-threaded tasks. The optimum IPC depends on the characteristics of the CMOS manufacturing process. Unfortunately, the design rules of the up-to-date CMOS processes are secret and in recent years the CPU manufacturers have published much less information about their designs than it was customary decades ago. Therefore, based on the publicly available information it is impossible to estimate which would be the optimum IPC for a CPU with many cores. Nevertheless, it is likely that the IPC of the big Apple cores is too high and even the IPC of the big Intel and AMD cores is likely to be too high. The IPC of the Zen 4c cores may be closer to optimal in the current technology, but the companies which design CPU cores probably cannot afford to explore enough of the design space to determine which would be a really optimum IPC.

_a_a_a_ 3y ago
> it is impossible to estimate which would be the optimum IPC for a CPU with many cores Weird comment. 'Optimum' can only be defined with reference to a given task. Otherwise it's like talking about the correct top speed for a car – F1 racer, or a little runaround?
- adrian_b 3y ago
  You are right, but in the context of CPU cores the normal criteria for optimization are the ratio between performance and energy consumption and the ratio between performance and price, where the price is supposed to be determined by the manufacturing cost, which in turn for a given manufacturing process is determined by die area, so the second ratio becomes the ratio between performance and die area. If economic criteria like money spent for the design are used for optimization, than it becomes pretty much impossible to compare the competing companies, because almost every CPU design might be considered to have an optimum IPC, no matter how bad it is, because it is the best that could be achieved within their budget, by their design team. Because Apple can sell expensive products, the die area and the cost of the manufacturing process had little importance for them. Because their products use only few cores, the area of one core was not constrained, because the total die area remained below the process limits, when the core area is multiplied by the number of cores. So their main optimization criterion has been the ratio between performance and energy consumption for a single core, without area per core and power dissipation per core constraints. In this case the IPC is not constrained, there is no optimization problem for determining the IPC, the higher IPC, the better. Therefore, unlike the designer of cores for a server CPU, Apple has designed the cores with the highest IPC that they could achieve within the project schedule and budget, in a given TSMC process.
  - _a_a_a_ 3y ago
    Cracking answer, thanks. Just a not-so-small question though, increasing IPC linearly exponentiates the complexity and therefore the price. Current CPUs like x86 already have enormous scheduling windows for OOO (something like 200 instructions) and similarly sized instruction retirement windows (the ROB I think). In your view, is throwing load of money at the problem a good solution? I feel it may come back and bite them later.
    - adrian_b 3y ago
      The problem is that what really counts for someone who purchases a CPU are the 2 optimization criteria that I have mentioned above, which determine how much money will be spent initially for buying it and how much money will be spent over its lifetime for its energy consumption, both directly and indirectly (for cooling, occupied volume, carrying weight). On the other hand, the customers, except for the biggest customers who might receive samples for in-house testing before purchasing, cannot estimate accurately those costs, because the vendors avoid to provide adequate information, but the customers must depend on things like published benchmarks and extrapolations from older systems. So the CPU vendors have the incentive to skew their designs to get good results in some popular benchmarks, even when this policy results in designs that are inferior at better criteria. For example, for many years Intel has included the secure hash extensions only in their Atom CPUs, even if they would have been more useful in their other CPUs. This was caused because Geekbench included a SHA subtest, the ARM CPUs already had SHA instructions and Intel wanted for their Atom CPUs to reach Geekbench scores competitive with ARM. Only after Zen has also added SHA, the Intel Core and Xeon CPUs have also implemented it. The desktop CPUs spend a lot of resources for obtaining the best scores in the most popular single-threaded benchmarks. While a responsive computer is very desirable, the truth is that whenever a computer with a 5-GHz CPU reacts slowly to user input, that is guaranteed to be caused by badly designed software. The multi-threaded performance is much more fundamental, because it has physical limits determined by the current CMOS technology and it is also the true limit for productivity when the computer is used with really optimized software. What I mean, is that targeting popular single-threaded benchmarks in order to promote sales can result in spending more resources and in much more complex CPU cores than in the case when the cores would be optimized only for objective criteria and they would be exploited by better software.
zozbot234 3y ago
> Therefore, for a CPU with many cores, like a server CPU, the highest IPC is not the best. Depends on the workload. Some are inherently serial and cannot use many cores effectively, these will benefit from a bigger core w/ more IPC.
- wtallis 3y ago
  Even among single-threaded tasks, some workloads offer high instruction level parallelism that can be exploited by a wide and slow core while others consist of long dependency chains that minimize instruction level parallelism and are better served by a more narrow core that can run at much higher clock speeds.

_a_a_a_ 3y ago

> it is impossible to estimate which would be the optimum IPC for a CPU with many cores Weird comment. 'Optimum' can only be defined with reference to a given task. Otherwise it's like talking about the correct top speed for a car – F1 racer, or a little runaround?

adrian_b 3y ago
You are right, but in the context of CPU cores the normal criteria for optimization are the ratio between performance and energy consumption and the ratio between performance and price, where the price is supposed to be determined by the manufacturing cost, which in turn for a given manufacturing process is determined by die area, so the second ratio becomes the ratio between performance and die area. If economic criteria like money spent for the design are used for optimization, than it becomes pretty much impossible to compare the competing companies, because almost every CPU design might be considered to have an optimum IPC, no matter how bad it is, because it is the best that could be achieved within their budget, by their design team. Because Apple can sell expensive products, the die area and the cost of the manufacturing process had little importance for them. Because their products use only few cores, the area of one core was not constrained, because the total die area remained below the process limits, when the core area is multiplied by the number of cores. So their main optimization criterion has been the ratio between performance and energy consumption for a single core, without area per core and power dissipation per core constraints. In this case the IPC is not constrained, there is no optimization problem for determining the IPC, the higher IPC, the better. Therefore, unlike the designer of cores for a server CPU, Apple has designed the cores with the highest IPC that they could achieve within the project schedule and budget, in a given TSMC process.
- _a_a_a_ 3y ago
  Cracking answer, thanks. Just a not-so-small question though, increasing IPC linearly exponentiates the complexity and therefore the price. Current CPUs like x86 already have enormous scheduling windows for OOO (something like 200 instructions) and similarly sized instruction retirement windows (the ROB I think). In your view, is throwing load of money at the problem a good solution? I feel it may come back and bite them later.
  - adrian_b 3y ago
    The problem is that what really counts for someone who purchases a CPU are the 2 optimization criteria that I have mentioned above, which determine how much money will be spent initially for buying it and how much money will be spent over its lifetime for its energy consumption, both directly and indirectly (for cooling, occupied volume, carrying weight). On the other hand, the customers, except for the biggest customers who might receive samples for in-house testing before purchasing, cannot estimate accurately those costs, because the vendors avoid to provide adequate information, but the customers must depend on things like published benchmarks and extrapolations from older systems. So the CPU vendors have the incentive to skew their designs to get good results in some popular benchmarks, even when this policy results in designs that are inferior at better criteria. For example, for many years Intel has included the secure hash extensions only in their Atom CPUs, even if they would have been more useful in their other CPUs. This was caused because Geekbench included a SHA subtest, the ARM CPUs already had SHA instructions and Intel wanted for their Atom CPUs to reach Geekbench scores competitive with ARM. Only after Zen has also added SHA, the Intel Core and Xeon CPUs have also implemented it. The desktop CPUs spend a lot of resources for obtaining the best scores in the most popular single-threaded benchmarks. While a responsive computer is very desirable, the truth is that whenever a computer with a 5-GHz CPU reacts slowly to user input, that is guaranteed to be caused by badly designed software. The multi-threaded performance is much more fundamental, because it has physical limits determined by the current CMOS technology and it is also the true limit for productivity when the computer is used with really optimized software. What I mean, is that targeting popular single-threaded benchmarks in order to promote sales can result in spending more resources and in much more complex CPU cores than in the case when the cores would be optimized only for objective criteria and they would be exploited by better software.

zozbot234 3y ago

> Therefore, for a CPU with many cores, like a server CPU, the highest IPC is not the best. Depends on the workload. Some are inherently serial and cannot use many cores effectively, these will benefit from a bigger core w/ more IPC.

wtallis 3y ago
Even among single-threaded tasks, some workloads offer high instruction level parallelism that can be exploited by a wide and slow core while others consist of long dependency chains that minimize instruction level parallelism and are better served by a more narrow core that can run at much higher clock speeds.