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Could you go a bit in more depth on what those features are? I thought it was comparable to what others are doing, but take that as a lack of knowledge on my pa

Could you go a bit in more depth on what those features are? I thought it was comparable to what others are doing, but take that as a lack of knowledge on my part.

ksec 3y ago
Namely Wide Decode Stage Design. My numbers may not be up to date but most x86 from AMD and Intel only has 3-4. Some of the recent **mount from Intel retrofitted with 6 stage ( I think, and you can count Zen 3 dong 8 with micro-ops but I dont think that is a fair comparison ). Apple have been on this design for at least 3 iterations or 6 years. Zen 5 will be a ground up x86 design with wide decode by default ( i.e not something bolted on ). It will probably take some learning curve for them as well. The only other wide decode stage design I am aware of is POWER10. But then we never have enough information about it to read through. And it isn't clear how well the latest x86 ISA fits in compared it AArch64 which is fairly clean without AArch32 baggage. The Anandtech article [1] on M1 goes over this. But again none of these are new. If you follow the Apple CPU Core design trend. And there are insane amount of smaller details that matters. And the industry are all trending on similar wide decode designs in terms of high performance core, from Cortex X4 and the up coming X5 to Qualcomm's Oryon core. I would envision in 4-5 years time, unless Apple has any other breakthrough. All Performance CPU Core design to be converging into something fairly similar from a high level. This also echo what was witnessed by a Chip And Cheese article. ( Which I dont have time to find out the link so people will have to do some digging themselves :) ) [1] https://www.anandtech.com/print/16226/apple-silicon-m1-a14-deep-dive https://www.anandtech.com/print/16226/apple-silicon-m1-a14-d...
- dzaima 3y ago
  x86 at least has it being more CISCy on its side, with a read/write potentially being inlined into another instruction (perhaps that's the only significant thing but it's still relatively meaningful). I'm sure intel & AMD know fully well that there's lots of benefit to decoding wider, it's just significantly more expensive to do so on x86 than it is on aarch64 and thus they spend silicon where it's more effective to do so.

Could you go a bit in more depth on what those features are? I thought it was comparable to what others are doing, but take that as a lack of knowledge on my part.

ksec 3y ago

Namely Wide Decode Stage Design. My numbers may not be up to date but most x86 from AMD and Intel only has 3-4. Some of the recent **mount from Intel retrofitted with 6 stage ( I think, and you can count Zen 3 dong 8 with micro-ops but I dont think that is a fair comparison ). Apple have been on this design for at least 3 iterations or 6 years. Zen 5 will be a ground up x86 design with wide decode by default ( i.e not something bolted on ). It will probably take some learning curve for them as well. The only other wide decode stage design I am aware of is POWER10. But then we never have enough information about it to read through. And it isn't clear how well the latest x86 ISA fits in compared it AArch64 which is fairly clean without AArch32 baggage. The Anandtech article [1] on M1 goes over this. But again none of these are new. If you follow the Apple CPU Core design trend. And there are insane amount of smaller details that matters. And the industry are all trending on similar wide decode designs in terms of high performance core, from Cortex X4 and the up coming X5 to Qualcomm's Oryon core. I would envision in 4-5 years time, unless Apple has any other breakthrough. All Performance CPU Core design to be converging into something fairly similar from a high level. This also echo what was witnessed by a Chip And Cheese article. ( Which I dont have time to find out the link so people will have to do some digging themselves :) ) [1] https://www.anandtech.com/print/16226/apple-silicon-m1-a14-deep-dive https://www.anandtech.com/print/16226/apple-silicon-m1-a14-d...

dzaima 3y ago
x86 at least has it being more CISCy on its side, with a read/write potentially being inlined into another instruction (perhaps that's the only significant thing but it's still relatively meaningful). I'm sure intel & AMD know fully well that there's lots of benefit to decoding wider, it's just significantly more expensive to do so on x86 than it is on aarch64 and thus they spend silicon where it's more effective to do so.