3 ms·

I like more how Apple does it: optimize for IPC.

ksec 3y ago
It is not like AMD or Intel doesn't optimise for IPC. ( Some would argue the proper term is PPC / Performance Per Clock or more precisely PPW performance per watts ) A lot of what Apple started doing with A12 ( or even planned well before A12 ) and finally known to the PC world with A14 / M1 will be coming to Zen 5 and Zen 6.
- spookie 3y ago
  Could you go a bit in more depth on what those features are? I thought it was comparable to what others are doing, but take that as a lack of knowledge on my part.
  - ksec 3y ago
    Namely Wide Decode Stage Design. My numbers may not be up to date but most x86 from AMD and Intel only has 3-4. Some of the recent **mount from Intel retrofitted with 6 stage ( I think, and you can count Zen 3 dong 8 with micro-ops but I dont think that is a fair comparison ). Apple have been on this design for at least 3 iterations or 6 years. Zen 5 will be a ground up x86 design with wide decode by default ( i.e not something bolted on ). It will probably take some learning curve for them as well. The only other wide decode stage design I am aware of is POWER10. But then we never have enough information about it to read through. And it isn't clear how well the latest x86 ISA fits in compared it AArch64 which is fairly clean without AArch32 baggage. The Anandtech article [1] on M1 goes over this. But again none of these are new. If you follow the Apple CPU Core design trend. And there are insane amount of smaller details that matters. And the industry are all trending on similar wide decode designs in terms of high performance core, from Cortex X4 and the up coming X5 to Qualcomm's Oryon core. I would envision in 4-5 years time, unless Apple has any other breakthrough. All Performance CPU Core design to be converging into something fairly similar from a high level. This also echo what was witnessed by a Chip And Cheese article. ( Which I dont have time to find out the link so people will have to do some digging themselves :) ) [1] https://www.anandtech.com/print/16226/apple-silicon-m1-a14-deep-dive https://www.anandtech.com/print/16226/apple-silicon-m1-a14-d...
    - dzaima 3y ago
      x86 at least has it being more CISCy on its side, with a read/write potentially being inlined into another instruction (perhaps that's the only significant thing but it's still relatively meaningful). I'm sure intel & AMD know fully well that there's lots of benefit to decoding wider, it's just significantly more expensive to do so on x86 than it is on aarch64 and thus they spend silicon where it's more effective to do so.
adrian_b 3y ago
Apple does not optimize for IPC. Apple has just designed the CPU cores with the highest IPC among all known until now. The highest IPC is the best choice for minimum energy consumption in a CPU with few cores, like a mobile phone or light laptop CPU, because it allows the same performance at a lower clock frequency. A higher IPC requires more transistors and more money spent for the design of the core. Apple has been rich enough to afford both the design cost and the cost of being able to use exclusively more advanced manufacturing processes. When the IPC is increased to very high values, the area and the power consumption are increased by greater factors than the increase in performance. Therefore, for a CPU with many cores, like a server CPU, the highest IPC is not the best. There will be a lower IPC that is better, because it allows packing more cores in a given chip area and a given thermal design power, leading to a higher aggregate performance for multi-threaded tasks. The optimum IPC depends on the characteristics of the CMOS manufacturing process. Unfortunately, the design rules of the up-to-date CMOS processes are secret and in recent years the CPU manufacturers have published much less information about their designs than it was customary decades ago. Therefore, based on the publicly available information it is impossible to estimate which would be the optimum IPC for a CPU with many cores. Nevertheless, it is likely that the IPC of the big Apple cores is too high and even the IPC of the big Intel and AMD cores is likely to be too high. The IPC of the Zen 4c cores may be closer to optimal in the current technology, but the companies which design CPU cores probably cannot afford to explore enough of the design space to determine which would be a really optimum IPC.
- _a_a_a_ 3y ago
  > it is impossible to estimate which would be the optimum IPC for a CPU with many cores Weird comment. 'Optimum' can only be defined with reference to a given task. Otherwise it's like talking about the correct top speed for a car – F1 racer, or a little runaround?
  - adrian_b 3y ago
    You are right, but in the context of CPU cores the normal criteria for optimization are the ratio between performance and energy consumption and the ratio between performance and price, where the price is supposed to be determined by the manufacturing cost, which in turn for a given manufacturing process is determined by die area, so the second ratio becomes the ratio between performance and die area. If economic criteria like money spent for the design are used for optimization, than it becomes pretty much impossible to compare the competing companies, because almost every CPU design might be considered to have an optimum IPC, no matter how bad it is, because it is the best that could be achieved within their budget, by their design team. Because Apple can sell expensive products, the die area and the cost of the manufacturing process had little importance for them. Because their products use only few cores, the area of one core was not constrained, because the total die area remained below the process limits, when the core area is multiplied by the number of cores. So their main optimization criterion has been the ratio between performance and energy consumption for a single core, without area per core and power dissipation per core constraints. In this case the IPC is not constrained, there is no optimization problem for determining the IPC, the higher IPC, the better. Therefore, unlike the designer of cores for a server CPU, Apple has designed the cores with the highest IPC that they could achieve within the project schedule and budget, in a given TSMC process.
Symmetry 3y ago
A core that actually optimized for IPC would run at very low clock rates to make sure you can do a round trip to RAM in a single clock cycle.

ksec 3y ago

It is not like AMD or Intel doesn't optimise for IPC. ( Some would argue the proper term is PPC / Performance Per Clock or more precisely PPW performance per watts ) A lot of what Apple started doing with A12 ( or even planned well before A12 ) and finally known to the PC world with A14 / M1 will be coming to Zen 5 and Zen 6.

spookie 3y ago
Could you go a bit in more depth on what those features are? I thought it was comparable to what others are doing, but take that as a lack of knowledge on my part.
- ksec 3y ago
  Namely Wide Decode Stage Design. My numbers may not be up to date but most x86 from AMD and Intel only has 3-4. Some of the recent **mount from Intel retrofitted with 6 stage ( I think, and you can count Zen 3 dong 8 with micro-ops but I dont think that is a fair comparison ). Apple have been on this design for at least 3 iterations or 6 years. Zen 5 will be a ground up x86 design with wide decode by default ( i.e not something bolted on ). It will probably take some learning curve for them as well. The only other wide decode stage design I am aware of is POWER10. But then we never have enough information about it to read through. And it isn't clear how well the latest x86 ISA fits in compared it AArch64 which is fairly clean without AArch32 baggage. The Anandtech article [1] on M1 goes over this. But again none of these are new. If you follow the Apple CPU Core design trend. And there are insane amount of smaller details that matters. And the industry are all trending on similar wide decode designs in terms of high performance core, from Cortex X4 and the up coming X5 to Qualcomm's Oryon core. I would envision in 4-5 years time, unless Apple has any other breakthrough. All Performance CPU Core design to be converging into something fairly similar from a high level. This also echo what was witnessed by a Chip And Cheese article. ( Which I dont have time to find out the link so people will have to do some digging themselves :) ) [1] https://www.anandtech.com/print/16226/apple-silicon-m1-a14-deep-dive https://www.anandtech.com/print/16226/apple-silicon-m1-a14-d...
  - dzaima 3y ago
    x86 at least has it being more CISCy on its side, with a read/write potentially being inlined into another instruction (perhaps that's the only significant thing but it's still relatively meaningful). I'm sure intel & AMD know fully well that there's lots of benefit to decoding wider, it's just significantly more expensive to do so on x86 than it is on aarch64 and thus they spend silicon where it's more effective to do so.

adrian_b 3y ago

Apple does not optimize for IPC. Apple has just designed the CPU cores with the highest IPC among all known until now. The highest IPC is the best choice for minimum energy consumption in a CPU with few cores, like a mobile phone or light laptop CPU, because it allows the same performance at a lower clock frequency. A higher IPC requires more transistors and more money spent for the design of the core. Apple has been rich enough to afford both the design cost and the cost of being able to use exclusively more advanced manufacturing processes. When the IPC is increased to very high values, the area and the power consumption are increased by greater factors than the increase in performance. Therefore, for a CPU with many cores, like a server CPU, the highest IPC is not the best. There will be a lower IPC that is better, because it allows packing more cores in a given chip area and a given thermal design power, leading to a higher aggregate performance for multi-threaded tasks. The optimum IPC depends on the characteristics of the CMOS manufacturing process. Unfortunately, the design rules of the up-to-date CMOS processes are secret and in recent years the CPU manufacturers have published much less information about their designs than it was customary decades ago. Therefore, based on the publicly available information it is impossible to estimate which would be the optimum IPC for a CPU with many cores. Nevertheless, it is likely that the IPC of the big Apple cores is too high and even the IPC of the big Intel and AMD cores is likely to be too high. The IPC of the Zen 4c cores may be closer to optimal in the current technology, but the companies which design CPU cores probably cannot afford to explore enough of the design space to determine which would be a really optimum IPC.

_a_a_a_ 3y ago
> it is impossible to estimate which would be the optimum IPC for a CPU with many cores Weird comment. 'Optimum' can only be defined with reference to a given task. Otherwise it's like talking about the correct top speed for a car – F1 racer, or a little runaround?
- adrian_b 3y ago
  You are right, but in the context of CPU cores the normal criteria for optimization are the ratio between performance and energy consumption and the ratio between performance and price, where the price is supposed to be determined by the manufacturing cost, which in turn for a given manufacturing process is determined by die area, so the second ratio becomes the ratio between performance and die area. If economic criteria like money spent for the design are used for optimization, than it becomes pretty much impossible to compare the competing companies, because almost every CPU design might be considered to have an optimum IPC, no matter how bad it is, because it is the best that could be achieved within their budget, by their design team. Because Apple can sell expensive products, the die area and the cost of the manufacturing process had little importance for them. Because their products use only few cores, the area of one core was not constrained, because the total die area remained below the process limits, when the core area is multiplied by the number of cores. So their main optimization criterion has been the ratio between performance and energy consumption for a single core, without area per core and power dissipation per core constraints. In this case the IPC is not constrained, there is no optimization problem for determining the IPC, the higher IPC, the better. Therefore, unlike the designer of cores for a server CPU, Apple has designed the cores with the highest IPC that they could achieve within the project schedule and budget, in a given TSMC process.

Symmetry 3y ago

A core that actually optimized for IPC would run at very low clock rates to make sure you can do a round trip to RAM in a single clock cycle.