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AMD's Mild Hybrid Strategy: Ryzen Z1 in Asus's ROG Ally

101 points by ingve 3y ago

DeathArrow 3y ago
I like more how Apple does it: optimize for IPC.
- ksec 3y ago
  It is not like AMD or Intel doesn't optimise for IPC. ( Some would argue the proper term is PPC / Performance Per Clock or more precisely PPW performance per watts ) A lot of what Apple started doing with A12 ( or even planned well before A12 ) and finally known to the PC world with A14 / M1 will be coming to Zen 5 and Zen 6.
  - spookie 3y ago
    Could you go a bit in more depth on what those features are? I thought it was comparable to what others are doing, but take that as a lack of knowledge on my part.
    - ksec 3y ago
      Namely Wide Decode Stage Design. My numbers may not be up to date but most x86 from AMD and Intel only has 3-4. Some of the recent **mount from Intel retrofitted with 6 stage ( I think, and you can count Zen 3 dong 8 with micro-ops but I dont think that is a fair comparison ). Apple have been on this design for at least 3 iterations or 6 years. Zen 5 will be a ground up x86 design with wide decode by default ( i.e not something bolted on ). It will probably take some learning curve for them as well. The only other wide decode stage design I am aware of is POWER10. But then we never have enough information about it to read through. And it isn't clear how well the latest x86 ISA fits in compared it AArch64 which is fairly clean without AArch32 baggage. The Anandtech article [1] on M1 goes over this. But again none of these are new. If you follow the Apple CPU Core design trend. And there are insane amount of smaller details that matters. And the industry are all trending on similar wide decode designs in terms of high performance core, from Cortex X4 and the up coming X5 to Qualcomm's Oryon core. I would envision in 4-5 years time, unless Apple has any other breakthrough. All Performance CPU Core design to be converging into something fairly similar from a high level. This also echo what was witnessed by a Chip And Cheese article. ( Which I dont have time to find out the link so people will have to do some digging themselves :) ) [1] https://www.anandtech.com/print/16226/apple-silicon-m1-a14-deep-dive https://www.anandtech.com/print/16226/apple-silicon-m1-a14-d...
      - dzaima 3y ago
        x86 at least has it being more CISCy on its side, with a read/write potentially being inlined into another instruction (perhaps that's the only significant thing but it's still relatively meaningful). I'm sure intel & AMD know fully well that there's lots of benefit to decoding wider, it's just significantly more expensive to do so on x86 than it is on aarch64 and thus they spend silicon where it's more effective to do so.
- adrian_b 3y ago
  Apple does not optimize for IPC. Apple has just designed the CPU cores with the highest IPC among all known until now. The highest IPC is the best choice for minimum energy consumption in a CPU with few cores, like a mobile phone or light laptop CPU, because it allows the same performance at a lower clock frequency. A higher IPC requires more transistors and more money spent for the design of the core. Apple has been rich enough to afford both the design cost and the cost of being able to use exclusively more advanced manufacturing processes. When the IPC is increased to very high values, the area and the power consumption are increased by greater factors than the increase in performance. Therefore, for a CPU with many cores, like a server CPU, the highest IPC is not the best. There will be a lower IPC that is better, because it allows packing more cores in a given chip area and a given thermal design power, leading to a higher aggregate performance for multi-threaded tasks. The optimum IPC depends on the characteristics of the CMOS manufacturing process. Unfortunately, the design rules of the up-to-date CMOS processes are secret and in recent years the CPU manufacturers have published much less information about their designs than it was customary decades ago. Therefore, based on the publicly available information it is impossible to estimate which would be the optimum IPC for a CPU with many cores. Nevertheless, it is likely that the IPC of the big Apple cores is too high and even the IPC of the big Intel and AMD cores is likely to be too high. The IPC of the Zen 4c cores may be closer to optimal in the current technology, but the companies which design CPU cores probably cannot afford to explore enough of the design space to determine which would be a really optimum IPC.
  - _a_a_a_ 3y ago
    > it is impossible to estimate which would be the optimum IPC for a CPU with many cores Weird comment. 'Optimum' can only be defined with reference to a given task. Otherwise it's like talking about the correct top speed for a car – F1 racer, or a little runaround?
    - adrian_b 3y ago
      You are right, but in the context of CPU cores the normal criteria for optimization are the ratio between performance and energy consumption and the ratio between performance and price, where the price is supposed to be determined by the manufacturing cost, which in turn for a given manufacturing process is determined by die area, so the second ratio becomes the ratio between performance and die area. If economic criteria like money spent for the design are used for optimization, than it becomes pretty much impossible to compare the competing companies, because almost every CPU design might be considered to have an optimum IPC, no matter how bad it is, because it is the best that could be achieved within their budget, by their design team. Because Apple can sell expensive products, the die area and the cost of the manufacturing process had little importance for them. Because their products use only few cores, the area of one core was not constrained, because the total die area remained below the process limits, when the core area is multiplied by the number of cores. So their main optimization criterion has been the ratio between performance and energy consumption for a single core, without area per core and power dissipation per core constraints. In this case the IPC is not constrained, there is no optimization problem for determining the IPC, the higher IPC, the better. Therefore, unlike the designer of cores for a server CPU, Apple has designed the cores with the highest IPC that they could achieve within the project schedule and budget, in a given TSMC process.
- Symmetry 3y ago
  A core that actually optimized for IPC would run at very low clock rates to make sure you can do a round trip to RAM in a single clock cycle.
xgstation 3y ago
This is interesting. The article mentioned Zen4c is architecture same to Zen4 but optimized for density running at lower frequency. Question here if anyone knows the answer: it seems like high frequency requires significantly more transistors? And is optimized for density also means less power consumption(assuming both zen4 and zen4c running at same frequency)?
- adrian_b 3y ago
  It may require more transistors in some places, e.g. in longer buffer chains needed to drive greater capacitances at higher frequencies, but it requires mostly bigger transistors in many places. According to AMD, both the big core and the small core use the same RTL design, but a different physical design, i.e. they use different libraries of standard cells (optimized either for high speed or for low area and low power consumption) and different layouts in the custom parts.
- scheme271 3y ago
  Yeah, I think high frequency requires more transistors to do buffering of signals. Also reducing the cache speeds and size allows simpler, smaller designs to be used. Finally, reduced frequencies mean that you don't need as high a voltage to force signals to go to 0 or 1 quickly so you need less power. All of this gives zen4c lower power consumption at the same frequency.
- yaantc 3y ago
  For a given process design kit (PDK), the synthesis tool will have a few different types of transistors. They correspond to different trade-offs between size and power on one hand, and speed on the other. The fastest the transistor, the bigger it is and the more it leaks (lower voltage threshold means faster switch time, but more leakage). For a given target frequency, the synthesis tool will always use the most efficient transistors it can. And the result is a mix, using the few available types. But the highest the frequency, the higher the proportion of faster and bigger transistors in the mix. This is the bird's eye view and very simplified, but hopefully enough to get the idea ;)
  - 3y ago
Dalewyn 3y ago
The article sidesteps the question of whether the OS scheduler can operate the differential cores effectively. The 7900X3D and 7950X3D became infamous for having less practical performance compared to their lower-tier brother, because the scheduler couldn't grasp which cores to schedule threads on. Does Zen4+Zen4c have a "Ryzen Thread Director" of sorts? Everything I've heard up to this point suggests it does not, relying completely on the OS scheduler to just figure it out (spoiler: it won't). AMD might make great hardware, but they consistently seem to give nary a damn about software.
- wtallis 3y ago
  Since the cores have the same microarchitecture and thus nearly identical performance characteristics aside from maximum frequency, the scheduling decisions are far simpler than for the 7950X3D or Intel's heterogeneous parts. It's only slightly more complex than Intel's more recent iterations of Turbo Boost, where 8-10 nominally identical cores have different maximum frequencies and one or two are identified as the fastest cores. The optimal scheduler behavior is: if a task needs more performance than a Zen 4c core can provide, run it on a full-sized Zen4 core. If it doesn't need that extra performance, run it on a Zen4c core to save power.
- kevingadd 3y ago
  A properly authored multi-core workload will balance across the cores even if some of them are slower via things like work-stealing, so while having a "thread director" to move the heaviest workloads onto the fastest cores would be nice, this architecture probably still works out pretty good even if it's less than perfect.
  - wmf 3y ago
    My real concern is about single-threaded workloads. The OS needs to schedule them on the higher-clocked cores. Apparently this has been in Windows for years and Linux 6.9 is getting it.
- binkHN 3y ago
  Not certain if it's related, but the recent p-state changes to the related code for AMD in the Linux scheduler has gotten smarter over the last several releases. It can pinpoint which cores are the fastest out similarly speced cores, based on manufacturing processes and related, and prefer those cores for tasks as they can run just a little bit faster.
ece 3y ago
Would've been cool if Asus had really tried to optimize the Ally around the Z1 with faster RAM, higher GPU clocks, and better battery life instead of offering the Z1 Extreme in an upsell. It's going for $400 now, which would've been real competition a year ago. Hard to recommend it now over the OLED Deck. Will be interesting to see AMD try this in consumer processors, with frame time graphs.
- theshackleford 3y ago
  Whilst in some ways I’d prefer OLED , the 120hz display with high nits output on the ally has been phenomenal for retro titles using BFI. In fact it’s been so good I don’t think I could give it up now. It’s a pity because in every other way, it’s not really that ideal for me. I’m a sucker for that motion resolution but. edited NITS not bits. My bad.
  - stavros 3y ago
    Why do you need 120 Hz for retro titles? Also, what's BFI?
    - theshackleford 3y ago
      You need 120hz minimum to be able to do BFI for a title pumping out at 60hz. BFI stands for "Black Frame Insertion" and it enhances motion resolution in LCD/OLED/Sample and Hold displays by inserting a black frame or blackout between regular frames. This has the result of reducing motion blur by shortening the time each frame is visible, making fast-moving content appear sharper and clearer. It effectively mimics in a way older CRT monitors, improving the perception of motion. Which for me is huge, because I still game on CRT's on the regular and LCD's abysmal handling of motion is a major detriment to me of my enjoyment of such things, especially for titles that were designed and produced for displays that had much clearer motion. It's a niche use case i'll admit, and i'd never claim otherwise, and it's not for everybody. But its funny that without that capability, id trade it in for an OLED deck tomorrow.
      - 3y ago
Dunedan 3y ago
> On the desktop scene, AMD’s Ryzen 7950X3D mixes cache configurations and has mild clock speed differences. For portable devices, the Ryzen Z1 here mixes cores with different physical designs and has larger clock speed deltas across the chip. AMD’s other consumer offerings do not use hybrid configurations. There are also desktop APUs using a combination of Zen 4 and Zen 4c cores (Ryzen 3 8300G, Ryzen 5 8500G), as well as other mobile CPUs doing the same (Ryzen 3 7440U, Ryzen 5 7545U).
- dheera 3y ago
  I hate these hybrid configurations, I recently rebuilt my desktop and jumped from Intel to AMD (7950X, not 7950X3D) specificially because I don't want a hybrid desktop CPU. All of Intel's 14th gen desktop offerings are hybrid. I hope AMD doesn't get on that bandwagon. I do a lot of highly parallelized image processing and preprocessing for machine learning and I don't want any cores holding other cores back.
  - bee_rider 3y ago
    It is hybrid but the only difference is that the little cores are clocked lower. It is pretty common for a CPU to have different clock speeds depending on how many cores are active (not to mention AVX clocks, so clock speed is just a thing that bounces around). This doesn’t seem drastically different.
  - belthesar 3y ago
    The interesting thing is that even on highly dense workloads, the benchmarks and real world tests are showing that these hybrid core architectures are doing surprisingly great things. I have more reading to do on the AMD side, so if you have more info than I take this with a grain of salt, but at least on the Intel side of the camp, the performance of a fully saturated E core is only slightly worse than its P core buddy, with 2x E cores meeting or exceeding the work output of a single P core + its hyperthread. Even if the only purpose for the E cores is to run OS and other background workloads while your big processing job is getting unfettered access to the P core array, I imagine you'd see pretty great gains here.
  - 3y ago
twotwotwo 3y ago
Like the post says near the end, this seems like at least partly the result of AMD not being the size of Intel or Apple, so not being able to have the staffing to create, validate, etc. two radically different large and small designs. So instead they tweak the synthesis of one design to lower max freq in exchange for area. There's less perf downside to using these cores, but less area/power upside. The perf impact of this or any hybrid design is also blunted by the power/cooling limits on non-hybrid designs: you can't afford to blast all the full-size cores on the chip at the max theoretical frequency at once anyway. Then, at the other end, lightly-threaded workloads can run mostly or only on the larger cores, so they're not heavily impacted either. If there's a way this ends up fun for consumer folks that follow this stuff, it'd probably be by allowing products w/more cores. In server chips using Zen 4c (Bergamo), more cores is explicitly the focus. On their desktop platform, one CCD of full-sized cores and one of smaller cores would allow a 24C two-CCD package. That would add another "flavor" of CPU, the way X3D is another "flavor", but I suspect there are applications where the extra throughput could help. No particular hints that this is part of their plans, to be clear.
- mastax 3y ago
  Another part of it is that AMD's Zen core is a much more area-efficient design than Intel's Raptor Cove (et. al.) core. Raptor Cove is 7.43mm^2 (Intel 7, Excluding L2/3 Cache) while Zen4 is 3.84 mm^2 (TSMC N5, Excluding L3 Cache). Intel 7 and TSMC N5 have comparable densities, though the numbers have changed over time and it depends on the transistor libraries used, etc. AMDs core is close to a clean-sheet redesign and, as Gelsinger has admitted, Intel has lost design leadership. The Zen4c core has a comparable size to the Gracemont E-cores, so they don't really need a separate design.
- beebeepka 3y ago
  It will be exciting to see two CCDs with big and c cores. However, Problem is, this many cores need bandwidth and two channel is hardly ideal. I hope AMD would at least double the channels on desktop and laptop. How else are they going to feed the future beefy APUs?
  - 3y ago
swozey 3y ago
I've owned a bunch of expensive ultrabooks, like $2500 samsung .. whatever it was with an aircraft aluminum frame and dell xps 13zs all with some form of intel low power laptop chip. They were all horrible to use. They constantly throttled to the point that I eventually ripped the dell open and repasted everything inside of it including de-lidding the cpu. I had to refoil and do a bunch of other stuff you wouldn't have to do on a desktop to repaste it was honestly nerve wracking and I've done all sorts of custom desktop pc water loop pasting stuff. Point being that it was an awful thing to have to do but the xps ran SO bad I did it. I gave the dell to my mom and I think I gave that samsung away too, I def don't have it anymore. And then I was done with intel ulv procs. That dell xps 13z was the prettiest, nicest form factor laptop I've used and it SUCKED and it was so sad. 2 months ago I bought an ally and I was absolutely terrified that it would run the same as those. It runs GREAT. It feels almost like using my amd ryzen 7700x, obviously not the same power but it's snappy and I don't mind using it as a laptop in bed at all. They did a great job. I have mine with a case on it that has a laptop keyboard/trackpad and it holds the screen up in bed, and I just use a travel mouse with it. I do wish the screen was larger though, so I wonder if I'd be happier with the Legion.
- wtallis 3y ago
  > including de-lidding the cpu As far as I'm aware, laptop CPUs haven't been packaged with an integrated heat spreader at any time since the ultrabook category was defined, so I have no idea what you are describing here.
  - swozey 3y ago
    I don't remember exactly what I did but I had to pry apart a bunch of copper heatspreader tubes and things like that, and I have a circle of copper heat spreader material and other weird stuff I haven't needed on other computers, I may not have delidded it but it was a very harrowing job. I was actually, as far as I know according to reddit and wherever I was reading dell xps forum stuff the first person to take it apart and do it. I wrote a tutorial about it I THINK on reddit. IIRC I had to remove the entire main board from the chassis and stuff. edit: Oh, I found a 2022 post about here on HN. I guess I didn't de-lid it. I took pictures of everything for the tutorial but no idea where that'd be, reddits search for dell 13z is worthless. Wow I didn't have that laptop very long. I absolutely hated using it, I wouldn't even use it in bed, and I DID get it replaced at one point hoping it was a bad laptop. https://news.ycombinator.com/item?id=31097858 https://news.ycombinator.com/item?id=31097858 Narrator voice: He did buy the $3500 macbook in the end edit2: Tutorial https://old.reddit.com/r/Dell/comments/vqz9wn/xps_13_2in1_9310_11th_gen_intel_thermal_repaste/ https://old.reddit.com/r/Dell/comments/vqz9wn/xps_13_2in1_93... This is giving me terrible flashbacks I even broke a few things, there were hidden screws holding board down you had to remove from the underside somehow or break everything when you lifted the board up. I had NO idea they were there and everything was super fragile.

101 points by ingve 3y ago

DeathArrow 3y ago

I like more how Apple does it: optimize for IPC.

ksec 3y ago
It is not like AMD or Intel doesn't optimise for IPC. ( Some would argue the proper term is PPC / Performance Per Clock or more precisely PPW performance per watts ) A lot of what Apple started doing with A12 ( or even planned well before A12 ) and finally known to the PC world with A14 / M1 will be coming to Zen 5 and Zen 6.
- spookie 3y ago
  Could you go a bit in more depth on what those features are? I thought it was comparable to what others are doing, but take that as a lack of knowledge on my part.
  - ksec 3y ago
    Namely Wide Decode Stage Design. My numbers may not be up to date but most x86 from AMD and Intel only has 3-4. Some of the recent **mount from Intel retrofitted with 6 stage ( I think, and you can count Zen 3 dong 8 with micro-ops but I dont think that is a fair comparison ). Apple have been on this design for at least 3 iterations or 6 years. Zen 5 will be a ground up x86 design with wide decode by default ( i.e not something bolted on ). It will probably take some learning curve for them as well. The only other wide decode stage design I am aware of is POWER10. But then we never have enough information about it to read through. And it isn't clear how well the latest x86 ISA fits in compared it AArch64 which is fairly clean without AArch32 baggage. The Anandtech article [1] on M1 goes over this. But again none of these are new. If you follow the Apple CPU Core design trend. And there are insane amount of smaller details that matters. And the industry are all trending on similar wide decode designs in terms of high performance core, from Cortex X4 and the up coming X5 to Qualcomm's Oryon core. I would envision in 4-5 years time, unless Apple has any other breakthrough. All Performance CPU Core design to be converging into something fairly similar from a high level. This also echo what was witnessed by a Chip And Cheese article. ( Which I dont have time to find out the link so people will have to do some digging themselves :) ) [1] https://www.anandtech.com/print/16226/apple-silicon-m1-a14-deep-dive https://www.anandtech.com/print/16226/apple-silicon-m1-a14-d...
    - dzaima 3y ago
      x86 at least has it being more CISCy on its side, with a read/write potentially being inlined into another instruction (perhaps that's the only significant thing but it's still relatively meaningful). I'm sure intel & AMD know fully well that there's lots of benefit to decoding wider, it's just significantly more expensive to do so on x86 than it is on aarch64 and thus they spend silicon where it's more effective to do so.
adrian_b 3y ago
Apple does not optimize for IPC. Apple has just designed the CPU cores with the highest IPC among all known until now. The highest IPC is the best choice for minimum energy consumption in a CPU with few cores, like a mobile phone or light laptop CPU, because it allows the same performance at a lower clock frequency. A higher IPC requires more transistors and more money spent for the design of the core. Apple has been rich enough to afford both the design cost and the cost of being able to use exclusively more advanced manufacturing processes. When the IPC is increased to very high values, the area and the power consumption are increased by greater factors than the increase in performance. Therefore, for a CPU with many cores, like a server CPU, the highest IPC is not the best. There will be a lower IPC that is better, because it allows packing more cores in a given chip area and a given thermal design power, leading to a higher aggregate performance for multi-threaded tasks. The optimum IPC depends on the characteristics of the CMOS manufacturing process. Unfortunately, the design rules of the up-to-date CMOS processes are secret and in recent years the CPU manufacturers have published much less information about their designs than it was customary decades ago. Therefore, based on the publicly available information it is impossible to estimate which would be the optimum IPC for a CPU with many cores. Nevertheless, it is likely that the IPC of the big Apple cores is too high and even the IPC of the big Intel and AMD cores is likely to be too high. The IPC of the Zen 4c cores may be closer to optimal in the current technology, but the companies which design CPU cores probably cannot afford to explore enough of the design space to determine which would be a really optimum IPC.
- _a_a_a_ 3y ago
  > it is impossible to estimate which would be the optimum IPC for a CPU with many cores Weird comment. 'Optimum' can only be defined with reference to a given task. Otherwise it's like talking about the correct top speed for a car – F1 racer, or a little runaround?
  - adrian_b 3y ago
    You are right, but in the context of CPU cores the normal criteria for optimization are the ratio between performance and energy consumption and the ratio between performance and price, where the price is supposed to be determined by the manufacturing cost, which in turn for a given manufacturing process is determined by die area, so the second ratio becomes the ratio between performance and die area. If economic criteria like money spent for the design are used for optimization, than it becomes pretty much impossible to compare the competing companies, because almost every CPU design might be considered to have an optimum IPC, no matter how bad it is, because it is the best that could be achieved within their budget, by their design team. Because Apple can sell expensive products, the die area and the cost of the manufacturing process had little importance for them. Because their products use only few cores, the area of one core was not constrained, because the total die area remained below the process limits, when the core area is multiplied by the number of cores. So their main optimization criterion has been the ratio between performance and energy consumption for a single core, without area per core and power dissipation per core constraints. In this case the IPC is not constrained, there is no optimization problem for determining the IPC, the higher IPC, the better. Therefore, unlike the designer of cores for a server CPU, Apple has designed the cores with the highest IPC that they could achieve within the project schedule and budget, in a given TSMC process.
Symmetry 3y ago
A core that actually optimized for IPC would run at very low clock rates to make sure you can do a round trip to RAM in a single clock cycle.

xgstation 3y ago

This is interesting. The article mentioned Zen4c is architecture same to Zen4 but optimized for density running at lower frequency. Question here if anyone knows the answer: it seems like high frequency requires significantly more transistors? And is optimized for density also means less power consumption(assuming both zen4 and zen4c running at same frequency)?

adrian_b 3y ago
It may require more transistors in some places, e.g. in longer buffer chains needed to drive greater capacitances at higher frequencies, but it requires mostly bigger transistors in many places. According to AMD, both the big core and the small core use the same RTL design, but a different physical design, i.e. they use different libraries of standard cells (optimized either for high speed or for low area and low power consumption) and different layouts in the custom parts.
scheme271 3y ago
Yeah, I think high frequency requires more transistors to do buffering of signals. Also reducing the cache speeds and size allows simpler, smaller designs to be used. Finally, reduced frequencies mean that you don't need as high a voltage to force signals to go to 0 or 1 quickly so you need less power. All of this gives zen4c lower power consumption at the same frequency.
yaantc 3y ago
For a given process design kit (PDK), the synthesis tool will have a few different types of transistors. They correspond to different trade-offs between size and power on one hand, and speed on the other. The fastest the transistor, the bigger it is and the more it leaks (lower voltage threshold means faster switch time, but more leakage). For a given target frequency, the synthesis tool will always use the most efficient transistors it can. And the result is a mix, using the few available types. But the highest the frequency, the higher the proportion of faster and bigger transistors in the mix. This is the bird's eye view and very simplified, but hopefully enough to get the idea ;)
- 3y ago

Dalewyn 3y ago

The article sidesteps the question of whether the OS scheduler can operate the differential cores effectively. The 7900X3D and 7950X3D became infamous for having less practical performance compared to their lower-tier brother, because the scheduler couldn't grasp which cores to schedule threads on. Does Zen4+Zen4c have a "Ryzen Thread Director" of sorts? Everything I've heard up to this point suggests it does not, relying completely on the OS scheduler to just figure it out (spoiler: it won't). AMD might make great hardware, but they consistently seem to give nary a damn about software.

wtallis 3y ago
Since the cores have the same microarchitecture and thus nearly identical performance characteristics aside from maximum frequency, the scheduling decisions are far simpler than for the 7950X3D or Intel's heterogeneous parts. It's only slightly more complex than Intel's more recent iterations of Turbo Boost, where 8-10 nominally identical cores have different maximum frequencies and one or two are identified as the fastest cores. The optimal scheduler behavior is: if a task needs more performance than a Zen 4c core can provide, run it on a full-sized Zen4 core. If it doesn't need that extra performance, run it on a Zen4c core to save power.
kevingadd 3y ago
A properly authored multi-core workload will balance across the cores even if some of them are slower via things like work-stealing, so while having a "thread director" to move the heaviest workloads onto the fastest cores would be nice, this architecture probably still works out pretty good even if it's less than perfect.
- wmf 3y ago
  My real concern is about single-threaded workloads. The OS needs to schedule them on the higher-clocked cores. Apparently this has been in Windows for years and Linux 6.9 is getting it.
binkHN 3y ago
Not certain if it's related, but the recent p-state changes to the related code for AMD in the Linux scheduler has gotten smarter over the last several releases. It can pinpoint which cores are the fastest out similarly speced cores, based on manufacturing processes and related, and prefer those cores for tasks as they can run just a little bit faster.

ece 3y ago

Would've been cool if Asus had really tried to optimize the Ally around the Z1 with faster RAM, higher GPU clocks, and better battery life instead of offering the Z1 Extreme in an upsell. It's going for $400 now, which would've been real competition a year ago. Hard to recommend it now over the OLED Deck. Will be interesting to see AMD try this in consumer processors, with frame time graphs.

theshackleford 3y ago
Whilst in some ways I’d prefer OLED , the 120hz display with high nits output on the ally has been phenomenal for retro titles using BFI. In fact it’s been so good I don’t think I could give it up now. It’s a pity because in every other way, it’s not really that ideal for me. I’m a sucker for that motion resolution but. edited NITS not bits. My bad.
- stavros 3y ago
  Why do you need 120 Hz for retro titles? Also, what's BFI?
  - theshackleford 3y ago
    You need 120hz minimum to be able to do BFI for a title pumping out at 60hz. BFI stands for "Black Frame Insertion" and it enhances motion resolution in LCD/OLED/Sample and Hold displays by inserting a black frame or blackout between regular frames. This has the result of reducing motion blur by shortening the time each frame is visible, making fast-moving content appear sharper and clearer. It effectively mimics in a way older CRT monitors, improving the perception of motion. Which for me is huge, because I still game on CRT's on the regular and LCD's abysmal handling of motion is a major detriment to me of my enjoyment of such things, especially for titles that were designed and produced for displays that had much clearer motion. It's a niche use case i'll admit, and i'd never claim otherwise, and it's not for everybody. But its funny that without that capability, id trade it in for an OLED deck tomorrow.
    - 3y ago

Dunedan 3y ago

> On the desktop scene, AMD’s Ryzen 7950X3D mixes cache configurations and has mild clock speed differences. For portable devices, the Ryzen Z1 here mixes cores with different physical designs and has larger clock speed deltas across the chip. AMD’s other consumer offerings do not use hybrid configurations. There are also desktop APUs using a combination of Zen 4 and Zen 4c cores (Ryzen 3 8300G, Ryzen 5 8500G), as well as other mobile CPUs doing the same (Ryzen 3 7440U, Ryzen 5 7545U).

dheera 3y ago
I hate these hybrid configurations, I recently rebuilt my desktop and jumped from Intel to AMD (7950X, not 7950X3D) specificially because I don't want a hybrid desktop CPU. All of Intel's 14th gen desktop offerings are hybrid. I hope AMD doesn't get on that bandwagon. I do a lot of highly parallelized image processing and preprocessing for machine learning and I don't want any cores holding other cores back.
- bee_rider 3y ago
  It is hybrid but the only difference is that the little cores are clocked lower. It is pretty common for a CPU to have different clock speeds depending on how many cores are active (not to mention AVX clocks, so clock speed is just a thing that bounces around). This doesn’t seem drastically different.
- belthesar 3y ago
  The interesting thing is that even on highly dense workloads, the benchmarks and real world tests are showing that these hybrid core architectures are doing surprisingly great things. I have more reading to do on the AMD side, so if you have more info than I take this with a grain of salt, but at least on the Intel side of the camp, the performance of a fully saturated E core is only slightly worse than its P core buddy, with 2x E cores meeting or exceeding the work output of a single P core + its hyperthread. Even if the only purpose for the E cores is to run OS and other background workloads while your big processing job is getting unfettered access to the P core array, I imagine you'd see pretty great gains here.
- 3y ago

twotwotwo 3y ago

Like the post says near the end, this seems like at least partly the result of AMD not being the size of Intel or Apple, so not being able to have the staffing to create, validate, etc. two radically different large and small designs. So instead they tweak the synthesis of one design to lower max freq in exchange for area. There's less perf downside to using these cores, but less area/power upside. The perf impact of this or any hybrid design is also blunted by the power/cooling limits on non-hybrid designs: you can't afford to blast all the full-size cores on the chip at the max theoretical frequency at once anyway. Then, at the other end, lightly-threaded workloads can run mostly or only on the larger cores, so they're not heavily impacted either. If there's a way this ends up fun for consumer folks that follow this stuff, it'd probably be by allowing products w/more cores. In server chips using Zen 4c (Bergamo), more cores is explicitly the focus. On their desktop platform, one CCD of full-sized cores and one of smaller cores would allow a 24C two-CCD package. That would add another "flavor" of CPU, the way X3D is another "flavor", but I suspect there are applications where the extra throughput could help. No particular hints that this is part of their plans, to be clear.

mastax 3y ago
Another part of it is that AMD's Zen core is a much more area-efficient design than Intel's Raptor Cove (et. al.) core. Raptor Cove is 7.43mm^2 (Intel 7, Excluding L2/3 Cache) while Zen4 is 3.84 mm^2 (TSMC N5, Excluding L3 Cache). Intel 7 and TSMC N5 have comparable densities, though the numbers have changed over time and it depends on the transistor libraries used, etc. AMDs core is close to a clean-sheet redesign and, as Gelsinger has admitted, Intel has lost design leadership. The Zen4c core has a comparable size to the Gracemont E-cores, so they don't really need a separate design.
beebeepka 3y ago
It will be exciting to see two CCDs with big and c cores. However, Problem is, this many cores need bandwidth and two channel is hardly ideal. I hope AMD would at least double the channels on desktop and laptop. How else are they going to feed the future beefy APUs?
- 3y ago

swozey 3y ago

I've owned a bunch of expensive ultrabooks, like $2500 samsung .. whatever it was with an aircraft aluminum frame and dell xps 13zs all with some form of intel low power laptop chip. They were all horrible to use. They constantly throttled to the point that I eventually ripped the dell open and repasted everything inside of it including de-lidding the cpu. I had to refoil and do a bunch of other stuff you wouldn't have to do on a desktop to repaste it was honestly nerve wracking and I've done all sorts of custom desktop pc water loop pasting stuff. Point being that it was an awful thing to have to do but the xps ran SO bad I did it. I gave the dell to my mom and I think I gave that samsung away too, I def don't have it anymore. And then I was done with intel ulv procs. That dell xps 13z was the prettiest, nicest form factor laptop I've used and it SUCKED and it was so sad. 2 months ago I bought an ally and I was absolutely terrified that it would run the same as those. It runs GREAT. It feels almost like using my amd ryzen 7700x, obviously not the same power but it's snappy and I don't mind using it as a laptop in bed at all. They did a great job. I have mine with a case on it that has a laptop keyboard/trackpad and it holds the screen up in bed, and I just use a travel mouse with it. I do wish the screen was larger though, so I wonder if I'd be happier with the Legion.

wtallis 3y ago
> including de-lidding the cpu As far as I'm aware, laptop CPUs haven't been packaged with an integrated heat spreader at any time since the ultrabook category was defined, so I have no idea what you are describing here.
- swozey 3y ago
  I don't remember exactly what I did but I had to pry apart a bunch of copper heatspreader tubes and things like that, and I have a circle of copper heat spreader material and other weird stuff I haven't needed on other computers, I may not have delidded it but it was a very harrowing job. I was actually, as far as I know according to reddit and wherever I was reading dell xps forum stuff the first person to take it apart and do it. I wrote a tutorial about it I THINK on reddit. IIRC I had to remove the entire main board from the chassis and stuff. edit: Oh, I found a 2022 post about here on HN. I guess I didn't de-lid it. I took pictures of everything for the tutorial but no idea where that'd be, reddits search for dell 13z is worthless. Wow I didn't have that laptop very long. I absolutely hated using it, I wouldn't even use it in bed, and I DID get it replaced at one point hoping it was a bad laptop. https://news.ycombinator.com/item?id=31097858 https://news.ycombinator.com/item?id=31097858 Narrator voice: He did buy the $3500 macbook in the end edit2: Tutorial https://old.reddit.com/r/Dell/comments/vqz9wn/xps_13_2in1_9310_11th_gen_intel_thermal_repaste/ https://old.reddit.com/r/Dell/comments/vqz9wn/xps_13_2in1_93... This is giving me terrible flashbacks I even broke a few things, there were hidden screws holding board down you had to remove from the underside somehow or break everything when you lifted the board up. I had NO idea they were there and everything was super fragile.