>> We may be getting close to the limit for 2D density, but have just barely started moving in the 3rd dimension. Nah, 3D is already well under way. Micron is

>> We may be getting close to the limit for 2D density, but have just barely started moving in the 3rd dimension. Nah, 3D is already well under way. Micron is stacking 232 layers of memory cells to get high density: https://www.electronicdesign.com/technologies/embedded/article/21247462/electronic-design-3d-nand-memory-chips-stacked-high-at-micron https://www.electronicdesign.com/technologies/embedded/artic... Flash memory is also increasing the number of bits per cell by essentially going analog. So those two thing are why you can get 2 TB on your keychain. Then AMD is doing their 3D V-cache, putting a bunch L3 or L4 cache on a die stacked on top of the CPU. The issue there is that both the CPU and cache dissipate too much heat to keep stacking higher much higher. GPUs are using HBM memory which is also stacked, but again power dissipation is going to limit how far that can go. Even in low end devices - Raspberry Pi - we've had DRAM stacked on top of the SoC die for many years now. 20 Years ago 3D was seen as a way to higher levels of integration once scaling came to an end, but it's already been happening in more and more places as the end of scaling is near. Innovations will continue to squeak out slowly for some time.