This is probably the right place to grumble about the fact that it took Intel until ~2020 to stop selling chips that still don't have AVX/AVX2 in them, a solid

This is probably the right place to grumble about the fact that it took Intel until ~2020 to stop selling chips that still don't have AVX/AVX2 in them, a solid decade and change after the tech was introduced. According to the steam software survey as of Feb24, there's still almost 8% of the market that thus doesn't have access to AVX2. Which for many practical purposes means falling back to SSE for everything unless you want the complexity of dynamically dispatching functions according to instruction set and the complexities of it (https://news.ycombinator.com/item?id=24577069 https://news.ycombinator.com/item?id=24577069). Even for significant performance, I usually do not. The reason that whole rant is relevant is that the trick in the article (which is simple and short) doesn't even have a cost in SSE code! For SSE you have to do a load and shuffle anyways since there is no lane broadcast instruction. (The set1_ps intrinsic hides this from you, since it will compile instead to a broadcast if you have set the compiler suitably). Since you're already shuffling, there's no downside to this trick, only reduced register pressure.