IMO it's hard to spot the "holes" for parameters in a module - for instance, in the logic-card project the instantiations of "LDOReg" end up setting values of o

IMO it's hard to spot the "holes" for parameters in a module - for instance, in the logic-card project the instantiations of "LDOReg" end up setting values of objects in "Vdiv" two abstraction layers down. https://github.com/Timot05/logic-card/blob/a63581636233dd1f9ed675f36ace672402fc562f/elec/src/ldo_reg.ato#L63-L69 https://github.com/Timot05/logic-card/blob/a63581636233dd1f9...