3 ms·
They make a big point of using HD-FEC rather than SD-FEC. To me, that makes no sense - the extra power usage of SD-FEC can be tiny, even at high data rates.
by londons_explore 3y ago
They make a big point of using HD-FEC rather than SD-FEC.
To me, that makes no sense - the extra power usage of SD-FEC can be tiny, even at high data rates. The FEC problem can be parallelized (if the protocol is designed for this) so it doesn't need to run at line rate too.
(SD-FEC lets you get substantially more data throughput in a given channel).
- aDfbrtVt 3y agoI can think of a number of cases where using a hard decision decoder can be a better choice. Power would be one factor and I would strongly disagree that the power delta between soft and hard codes at these data rates is small. Unfortunately, I can not find any public data to back up that claim for what appear (based on coding gain and overhead) an HD-FEC using RS and a SD-FEC using braided BCH or LDPC. Other factors can include reduced routing complexity and area requirements of HD since you have to shuffle around soft information. Extra die space is expensive so you want to avoid it if possible. However, I think the most likely is the latency reduction you get when using HD-FEC. I know that some applications of microwave links are extremely latency sensitive, could be that this research is targeting one of those applications.