7 ms·

There are a few: If you need rapid, real time responses to external signals, the faster clocked 8 bitters are excellent! Many chips can get into an interrupt

There are a few: If you need rapid, real time responses to external signals, the faster clocked 8 bitters are excellent! Many chips can get into an interrupt service routine in just a handful of cycles. In tandem with this, these devices can pack a lot of logic into a small amount of code. From Dallas Semi: Our 1 clock-per-machine-cycle processors reached a remarkable performance goal—1 clock-per-machine-cycle, currently at 33 million instructions per second (MIPS). From Silicon Labs: The proven 8051 core received a welcome second wind when its architecture lost patent protection in 1998. [...] The original Intel 8051 core took 12 cycles to execute 1 instruction; thus, at 12 MHz, it ran at 1million instructions per second (1 MIP). In contrast, a 100 MHz Silicon Labs 8051 core will run at 100 MIPS or 100 times faster than the classic 8051 at a frequency that is only about 8x the classic 8051’s frequency. That's really fast, when it comes to responding to external events! Say one needs to read an incoming data stream, or control something moving at a high rate of speed. Both of these tasks depend on a device that can sense and respond in as close to real time as things get. Large, production proven, time tested code bodies. 6502, 8051, z80, etc... all have a ton of library code that's not difficult to understand and make use of. Often, these 8 bit designs can run on crazy low power, or operate very efficiently at full speed. Licensing isn't generally an issue. Adding a well documented and production proven 8 bit core to a specialized design works pretty well! Often, the custom hardware on chip does the heavy lifting, leaving UX and control tasks, both of which are easy and lean enough for 8 bits of CPU to make sense. The last thing I would put here is subjective, but ease of development can be an advantage, but it depends on the developer. Once someone has bootstrapped themselves onto 8 bit computing, the constraints on development both limit possible application scope and with that limit comes ease of development. When used to their strengths, simple chips like these are easy to develop for. It's possible for one person to completely understand a device and with that understanding fully exploit it.

nullc 3y ago
I wonder what the limit of computing power per joule is with current technology, assuming you were freely able to change the architecture. For example, perhaps you wouldn't use an integer instruction pointer, because a full adder to increment it is expensive. Instead you could use a LFSR where each increment requires only a couple xor gates and some wires. But it would mean that your code would have to be scattered in memory in a funny order. No problem for a smart assembler. How much computing power could you drive from a device powered by nothing other than ambient RF?
- dmitrygr 3y ago
  The thing you describe about replacing PC with an LFSR has actually been done, to simplify the silicon. Some very cheap 4-bit micro controllers, often used for TV Remotes, in fact, do this.
- ddingus 3y ago
  I think of this too. And I break it down into ads and operations. An ad is simply summing two inputs of some kind. In operation, might be a change of state or an input coming online or going away. Something analogous to the bit operations and or not exclusive or and friends. With all the physics talk of information being fundamental, I suspect we will find both an upper bound and a lower bound. The upper bound will be something like compute power per volume divided by energy or some similar construct. Basically you can only pack so much information and so many operations into a given region of space and energy level possible for that energy for that region of space to contain. The lower bound might be something like the plank constant for computation. What's the smallest unit of space and energy level that can support an add, for example. It's interesting to think about. Sorry for the typos I used voice dictation on this one
- crotchfire 3y ago
  ... and adding an integer to a pointer would be hellaciously expensive. If you have the foundry SPICE models you can calculate these kinds of lower-limit values. I did this for 45nm a long time ago and vaguely recall getting numbers down in the double-digit femtojoule range for 32-bit addition, measuring only transistor R+C. But the transistors don't really cost anything; all the CV^2 is in charging and discharging the wires. And the "C" is totally geometry-dependent. It's not like software -- at least not when you're pushing all the limits -- everything affects everything else.
  - nullc 3y ago
    > ... and adding an integer to a pointer would be hellaciously expensive. Fair, though if it were only the PC and instruction memory that were permuted that isn't much of an issue. It's not that bad the circuit looks more like a multiplier rather than an adder. (search term would be LFSR fast-forward or jump-ahead). PC is updated presumably on every cycle, while adding an an integer to it is probably a rare operation (just don't use computed jumps...).
iamflimflam1 3y ago
Interesting - I’ve been playing with some SD Card to USB interface ICs and almost all of them include an 8051 core.
guenthert 3y ago
I'd think, if you need rapid, real time response to external signals, you don't use interrupts, since then you usually need it to be deterministic as well. Either use 'nother micro, a spare core, given specialized hardware (e.g. the PRUs in TI's sitara MCUs, the PIO of RP2040, P8X32A) or roll your own (these days probably using FPGAs).
- SomeoneFromCA 3y ago
  You are wrong, as polling always introduces jitter (due indeterminacy of the event arriving moment between the last entry to the polling loop and the comparison operation). If you want really precise timing while reacting to external event is to sit in "halt" state, with interesting interrupts enabled.
  - deleted 3y ago
    [deleted]
- ddingus 3y ago
  Another micro = big BOM cost increase Another core = overall device cost likely unnecessary. Both blow the power budget up. Regarding determinism, relative to what? An interrupt will, or can be very consistent relative to the signal. Polling jitters relative to the same signal. That may not be desirable. Now, I did see you mention a Propeller chip! The first chip worked as you describe and it is beautiful. There are good reasons why interrupts were added to the second generation chip. They are mostly the reasons found in this discussion. I was a part of the P2 development. We had a TON of discussion on this topic. Fascinating. Let me share an observation: Many interrupt systems end up overloaded. One ends up writing a mini operating system to manage all the desired outcomes! And that can be a mess for sure. In the P2 chip, a couple things were done to help with all that: One is a priority and event system. Events trigger interrupts, and those break the program flow due to early implementation choices made that simplified the chip and made the power budget sane. There are three priority levels and 16 events that trigger on incoming signals as well as on chip events and other core on chip. The other was polling modes so one can wait and employ whichever mode made the most sense. Finally, interrupts happen after instructions complete. Doing this came with some controversy! But, it seriously simplified the chip and helped to draw the lines where the developer has choices to make and good options to make them.
deleted 3y ago
[deleted]

nullc 3y ago

I wonder what the limit of computing power per joule is with current technology, assuming you were freely able to change the architecture. For example, perhaps you wouldn't use an integer instruction pointer, because a full adder to increment it is expensive. Instead you could use a LFSR where each increment requires only a couple xor gates and some wires. But it would mean that your code would have to be scattered in memory in a funny order. No problem for a smart assembler. How much computing power could you drive from a device powered by nothing other than ambient RF?

dmitrygr 3y ago
The thing you describe about replacing PC with an LFSR has actually been done, to simplify the silicon. Some very cheap 4-bit micro controllers, often used for TV Remotes, in fact, do this.
ddingus 3y ago
I think of this too. And I break it down into ads and operations. An ad is simply summing two inputs of some kind. In operation, might be a change of state or an input coming online or going away. Something analogous to the bit operations and or not exclusive or and friends. With all the physics talk of information being fundamental, I suspect we will find both an upper bound and a lower bound. The upper bound will be something like compute power per volume divided by energy or some similar construct. Basically you can only pack so much information and so many operations into a given region of space and energy level possible for that energy for that region of space to contain. The lower bound might be something like the plank constant for computation. What's the smallest unit of space and energy level that can support an add, for example. It's interesting to think about. Sorry for the typos I used voice dictation on this one
crotchfire 3y ago
... and adding an integer to a pointer would be hellaciously expensive. If you have the foundry SPICE models you can calculate these kinds of lower-limit values. I did this for 45nm a long time ago and vaguely recall getting numbers down in the double-digit femtojoule range for 32-bit addition, measuring only transistor R+C. But the transistors don't really cost anything; all the CV^2 is in charging and discharging the wires. And the "C" is totally geometry-dependent. It's not like software -- at least not when you're pushing all the limits -- everything affects everything else.
- nullc 3y ago
  > ... and adding an integer to a pointer would be hellaciously expensive. Fair, though if it were only the PC and instruction memory that were permuted that isn't much of an issue. It's not that bad the circuit looks more like a multiplier rather than an adder. (search term would be LFSR fast-forward or jump-ahead). PC is updated presumably on every cycle, while adding an an integer to it is probably a rare operation (just don't use computed jumps...).

iamflimflam1 3y ago

Interesting - I’ve been playing with some SD Card to USB interface ICs and almost all of them include an 8051 core.

guenthert 3y ago

I'd think, if you need rapid, real time response to external signals, you don't use interrupts, since then you usually need it to be deterministic as well. Either use 'nother micro, a spare core, given specialized hardware (e.g. the PRUs in TI's sitara MCUs, the PIO of RP2040, P8X32A) or roll your own (these days probably using FPGAs).

SomeoneFromCA 3y ago
You are wrong, as polling always introduces jitter (due indeterminacy of the event arriving moment between the last entry to the polling loop and the comparison operation). If you want really precise timing while reacting to external event is to sit in "halt" state, with interesting interrupts enabled.
- deleted 3y ago
  [deleted]
ddingus 3y ago
Another micro = big BOM cost increase Another core = overall device cost likely unnecessary. Both blow the power budget up. Regarding determinism, relative to what? An interrupt will, or can be very consistent relative to the signal. Polling jitters relative to the same signal. That may not be desirable. Now, I did see you mention a Propeller chip! The first chip worked as you describe and it is beautiful. There are good reasons why interrupts were added to the second generation chip. They are mostly the reasons found in this discussion. I was a part of the P2 development. We had a TON of discussion on this topic. Fascinating. Let me share an observation: Many interrupt systems end up overloaded. One ends up writing a mini operating system to manage all the desired outcomes! And that can be a mess for sure. In the P2 chip, a couple things were done to help with all that: One is a priority and event system. Events trigger interrupts, and those break the program flow due to early implementation choices made that simplified the chip and made the power budget sane. There are three priority levels and 16 events that trigger on incoming signals as well as on chip events and other core on chip. The other was polling modes so one can wait and employ whichever mode made the most sense. Finally, interrupts happen after instructions complete. Doing this came with some controversy! But, it seriously simplified the chip and helped to draw the lines where the developer has choices to make and good options to make them.

deleted 3y ago

[deleted]