6 ms·

Is there an advantage to a 300MHz 8051 vs a Cortex M0? Predated their existence? I know there’s a lot of 8051 tooling but I’m only a dabbler in microcontroller

Is there an advantage to a 300MHz 8051 vs a Cortex M0? Predated their existence? I know there’s a lot of 8051 tooling but I’m only a dabbler in microcontrollers and it seems like AVRs and M0/M3s have taken the place of PICs and 8051s in hobby world.

dmitrygr 3y ago
8051 has no cost to license and if you are mostly using an accelerator to decode mp3, then the servicing of it is simple enough. Why rewrite the code you already have (from before cortex-m0 existed) or redesign the accelerator you already have?
ddingus 3y ago
There are a few: If you need rapid, real time responses to external signals, the faster clocked 8 bitters are excellent! Many chips can get into an interrupt service routine in just a handful of cycles. In tandem with this, these devices can pack a lot of logic into a small amount of code. From Dallas Semi: Our 1 clock-per-machine-cycle processors reached a remarkable performance goal—1 clock-per-machine-cycle, currently at 33 million instructions per second (MIPS). From Silicon Labs: The proven 8051 core received a welcome second wind when its architecture lost patent protection in 1998. [...] The original Intel 8051 core took 12 cycles to execute 1 instruction; thus, at 12 MHz, it ran at 1million instructions per second (1 MIP). In contrast, a 100 MHz Silicon Labs 8051 core will run at 100 MIPS or 100 times faster than the classic 8051 at a frequency that is only about 8x the classic 8051’s frequency. That's really fast, when it comes to responding to external events! Say one needs to read an incoming data stream, or control something moving at a high rate of speed. Both of these tasks depend on a device that can sense and respond in as close to real time as things get. Large, production proven, time tested code bodies. 6502, 8051, z80, etc... all have a ton of library code that's not difficult to understand and make use of. Often, these 8 bit designs can run on crazy low power, or operate very efficiently at full speed. Licensing isn't generally an issue. Adding a well documented and production proven 8 bit core to a specialized design works pretty well! Often, the custom hardware on chip does the heavy lifting, leaving UX and control tasks, both of which are easy and lean enough for 8 bits of CPU to make sense. The last thing I would put here is subjective, but ease of development can be an advantage, but it depends on the developer. Once someone has bootstrapped themselves onto 8 bit computing, the constraints on development both limit possible application scope and with that limit comes ease of development. When used to their strengths, simple chips like these are easy to develop for. It's possible for one person to completely understand a device and with that understanding fully exploit it.
- nullc 3y ago
  I wonder what the limit of computing power per joule is with current technology, assuming you were freely able to change the architecture. For example, perhaps you wouldn't use an integer instruction pointer, because a full adder to increment it is expensive. Instead you could use a LFSR where each increment requires only a couple xor gates and some wires. But it would mean that your code would have to be scattered in memory in a funny order. No problem for a smart assembler. How much computing power could you drive from a device powered by nothing other than ambient RF?
  - dmitrygr 3y ago
    The thing you describe about replacing PC with an LFSR has actually been done, to simplify the silicon. Some very cheap 4-bit micro controllers, often used for TV Remotes, in fact, do this.
  - ddingus 3y ago
    I think of this too. And I break it down into ads and operations. An ad is simply summing two inputs of some kind. In operation, might be a change of state or an input coming online or going away. Something analogous to the bit operations and or not exclusive or and friends. With all the physics talk of information being fundamental, I suspect we will find both an upper bound and a lower bound. The upper bound will be something like compute power per volume divided by energy or some similar construct. Basically you can only pack so much information and so many operations into a given region of space and energy level possible for that energy for that region of space to contain. The lower bound might be something like the plank constant for computation. What's the smallest unit of space and energy level that can support an add, for example. It's interesting to think about. Sorry for the typos I used voice dictation on this one
  - crotchfire 3y ago
    ... and adding an integer to a pointer would be hellaciously expensive. If you have the foundry SPICE models you can calculate these kinds of lower-limit values. I did this for 45nm a long time ago and vaguely recall getting numbers down in the double-digit femtojoule range for 32-bit addition, measuring only transistor R+C. But the transistors don't really cost anything; all the CV^2 is in charging and discharging the wires. And the "C" is totally geometry-dependent. It's not like software -- at least not when you're pushing all the limits -- everything affects everything else.
pclmulqdq 3y ago
M0s have taken the place of many 8051s in the "pro" world as well. There's still the niche that sibling comments have mentioned, but a lot of "default small MCUs" for new projects used to be 8051s and are now M0s.
addaon 3y ago
Besides the other comments, you can get 8051s at much lower power than M0s... think 1 picojoule per (8 bit) op vs 10 picojoules per (32 bit) op, give or take. It's pretty common to see 8051s in the low power zone of microcontrollers that also have one or more 32 bit cores on them. Generally the low power zone (including the 8051) can be run off an external clock (so 25 MHz - 100 MHz) in the 1 mW range, or can be run off an RC oscillator at a lower speed (like 7 ± 3 MHz) in the 100 µA range, both of which usefully extend the ability of the system to monitor for wake events and decide when to bring those Arm big boys on line. Some can even take the 8051 down to your 32 kHz real time clock for < 40 µA operation.
- RetroTechie 3y ago
  > Some can even take the 8051 down to your 32 kHz real time clock for < 40 µA operation. Isn't that a somewhat common ability for µC's? Allowing for very low power standby, RTC functionality & doing useful work at a higher speed?
  - addaon 3y ago
    Somewhat... I more often see the ability to run some fixed-function blocks (RTC, as you mentioned; also ADC running scheduled conversions with a digital comparator on conversion calling interrupt, as an example) running at this low a clock, with the model being that these low-speed peripherals wake up something else. Having the ability to run a useful set of peripherals /and/ do arbitrary very slow computations to decide about changing clock isn't universal. As an example, even if you had that capability, if you wanted to wake on a complicated condition of an ADC read, you might end up lower total energy use to wake up on the ADC conversion to the RC filter low-MHz speed, do the your computation, and either go back to sleep or continue to wake further, rather than do the computation itself at 32 kHz -- and certainly the former could be lower latency, depending on the complexity of computation.

dmitrygr 3y ago

8051 has no cost to license and if you are mostly using an accelerator to decode mp3, then the servicing of it is simple enough. Why rewrite the code you already have (from before cortex-m0 existed) or redesign the accelerator you already have?

ddingus 3y ago

There are a few: If you need rapid, real time responses to external signals, the faster clocked 8 bitters are excellent! Many chips can get into an interrupt service routine in just a handful of cycles. In tandem with this, these devices can pack a lot of logic into a small amount of code. From Dallas Semi: Our 1 clock-per-machine-cycle processors reached a remarkable performance goal—1 clock-per-machine-cycle, currently at 33 million instructions per second (MIPS). From Silicon Labs: The proven 8051 core received a welcome second wind when its architecture lost patent protection in 1998. [...] The original Intel 8051 core took 12 cycles to execute 1 instruction; thus, at 12 MHz, it ran at 1million instructions per second (1 MIP). In contrast, a 100 MHz Silicon Labs 8051 core will run at 100 MIPS or 100 times faster than the classic 8051 at a frequency that is only about 8x the classic 8051’s frequency. That's really fast, when it comes to responding to external events! Say one needs to read an incoming data stream, or control something moving at a high rate of speed. Both of these tasks depend on a device that can sense and respond in as close to real time as things get. Large, production proven, time tested code bodies. 6502, 8051, z80, etc... all have a ton of library code that's not difficult to understand and make use of. Often, these 8 bit designs can run on crazy low power, or operate very efficiently at full speed. Licensing isn't generally an issue. Adding a well documented and production proven 8 bit core to a specialized design works pretty well! Often, the custom hardware on chip does the heavy lifting, leaving UX and control tasks, both of which are easy and lean enough for 8 bits of CPU to make sense. The last thing I would put here is subjective, but ease of development can be an advantage, but it depends on the developer. Once someone has bootstrapped themselves onto 8 bit computing, the constraints on development both limit possible application scope and with that limit comes ease of development. When used to their strengths, simple chips like these are easy to develop for. It's possible for one person to completely understand a device and with that understanding fully exploit it.

nullc 3y ago
I wonder what the limit of computing power per joule is with current technology, assuming you were freely able to change the architecture. For example, perhaps you wouldn't use an integer instruction pointer, because a full adder to increment it is expensive. Instead you could use a LFSR where each increment requires only a couple xor gates and some wires. But it would mean that your code would have to be scattered in memory in a funny order. No problem for a smart assembler. How much computing power could you drive from a device powered by nothing other than ambient RF?
- dmitrygr 3y ago
  The thing you describe about replacing PC with an LFSR has actually been done, to simplify the silicon. Some very cheap 4-bit micro controllers, often used for TV Remotes, in fact, do this.
- ddingus 3y ago
  I think of this too. And I break it down into ads and operations. An ad is simply summing two inputs of some kind. In operation, might be a change of state or an input coming online or going away. Something analogous to the bit operations and or not exclusive or and friends. With all the physics talk of information being fundamental, I suspect we will find both an upper bound and a lower bound. The upper bound will be something like compute power per volume divided by energy or some similar construct. Basically you can only pack so much information and so many operations into a given region of space and energy level possible for that energy for that region of space to contain. The lower bound might be something like the plank constant for computation. What's the smallest unit of space and energy level that can support an add, for example. It's interesting to think about. Sorry for the typos I used voice dictation on this one
- crotchfire 3y ago
  ... and adding an integer to a pointer would be hellaciously expensive. If you have the foundry SPICE models you can calculate these kinds of lower-limit values. I did this for 45nm a long time ago and vaguely recall getting numbers down in the double-digit femtojoule range for 32-bit addition, measuring only transistor R+C. But the transistors don't really cost anything; all the CV^2 is in charging and discharging the wires. And the "C" is totally geometry-dependent. It's not like software -- at least not when you're pushing all the limits -- everything affects everything else.

pclmulqdq 3y ago

M0s have taken the place of many 8051s in the "pro" world as well. There's still the niche that sibling comments have mentioned, but a lot of "default small MCUs" for new projects used to be 8051s and are now M0s.

addaon 3y ago

Besides the other comments, you can get 8051s at much lower power than M0s... think 1 picojoule per (8 bit) op vs 10 picojoules per (32 bit) op, give or take. It's pretty common to see 8051s in the low power zone of microcontrollers that also have one or more 32 bit cores on them. Generally the low power zone (including the 8051) can be run off an external clock (so 25 MHz - 100 MHz) in the 1 mW range, or can be run off an RC oscillator at a lower speed (like 7 ± 3 MHz) in the 100 µA range, both of which usefully extend the ability of the system to monitor for wake events and decide when to bring those Arm big boys on line. Some can even take the 8051 down to your 32 kHz real time clock for < 40 µA operation.

RetroTechie 3y ago
> Some can even take the 8051 down to your 32 kHz real time clock for < 40 µA operation. Isn't that a somewhat common ability for µC's? Allowing for very low power standby, RTC functionality & doing useful work at a higher speed?
- addaon 3y ago
  Somewhat... I more often see the ability to run some fixed-function blocks (RTC, as you mentioned; also ADC running scheduled conversions with a digital comparator on conversion calling interrupt, as an example) running at this low a clock, with the model being that these low-speed peripherals wake up something else. Having the ability to run a useful set of peripherals /and/ do arbitrary very slow computations to decide about changing clock isn't universal. As an example, even if you had that capability, if you wanted to wake on a complicated condition of an ADC read, you might end up lower total energy use to wake up on the ADC conversion to the RC filter low-MHz speed, do the your computation, and either go back to sleep or continue to wake further, rather than do the computation itself at 32 kHz -- and certainly the former could be lower latency, depending on the complexity of computation.