The traditional computer chip will have a power draw proportional to frequency and the square of voltage, which itself must be increased to control delay and ra

The traditional computer chip will have a power draw proportional to frequency and the square of voltage, which itself must be increased to control delay and raise frequency: P ∝ C×V²×f So if you are ready to accept a lower speed per core, the power draw can be controlled and you won't get a toaster. One difficulty would be that modern technological nodes have high leakage and dissipate power even when they are not switching, making it more advantageous to clock aggressively, finish the computation as fast as possible and cut the power on that entire circuit for the remainder of the timer slot ("race to idle"), as opposed to reducing the frequency and prolonging the "on" phase. But that's a deliberate design choice, knowing the chip will be cut out and fitted with a substantial thermal solution. Wafer level power draw it's definitely something you can control at the design stage.